MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1606

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Unified DMA Block Guide
26.2.2.31.23.10
when a DMA detects an error during the data transfer.
26.2.2.31.23.11
Underflow error. This bit is written by the uDMA. This bit indicates that the MAC reported
an underfow error on transmit.
26.2.2.31.23.12
Excess Collision error. This bit is written by the uDMA. This bit indicates that the MAC
reported an excess collision error on transmit. This bit is only valid when the L-bit is set.
26.2.2.31.23.13
Frame with error. This bit is written by the uDMA. This bit indicates that the MAC reported
that the uDMA reported an error when providing the packet. This bit is only valid when the
L-bit is set.
26.2.2.31.23.14
Late collision error. This bit is written by the uDMA. This bit indicates that the MAC
reported that there was a Late Collision on transmit. This bit is only valid when the L-bit
is set.
26.2.2.31.23.15
Overfow error. This bit is written by the uDMA. This bit indicates that the MAC reported
that there was a FIFO overfow condition on transmit. This bit is only valid when the L-bit
is set.
26.2.2.31.23.16
Timestamp error. This bit is written by the uDMA. This bit indicates that the MAC reported
a different frame type then a timestamp frame. This bit is only valid when the L-bit is set.
26.2.2.31.23.17
BD data has been updated by uDMA. This bit is written by the user (=0) and uDMA (=1).
26.2.2.31.23.18
This value is written by the uDMA when switch is in Bypass mode. It is only valid if the
L-bit is set.
1606
Offset + A Bit 14 "-"
This bit is not used (reserved) since the uDMA will abort the operation
Offset + A Bit 13 "UE"
Offset + A Bit 12 "EE"
Offset + A Bit 11 "FE"
Offset + A Bit 10 "LCE"
Offset + A Bit 9 "OE"
Offset + A Bit 8 "TSE"
Offset + 0x10 - Bit 15 "BDU"
Last Buffer Descriptor Update Done. This bit indicates that all the last
1588 Timestamp [31:0]
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.