MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2210

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Operation
of the 32-bit HW_SAIF_DATA register. Writes place PCM values at the top of the FIFOs,
and reads take them from the bottom of the FIFOs. Each FIFO is used to store different sets
of left/right channel pairs. FIFO1 stores the stereo or front channels, FIFO2 the surround
or rear channels, and FIFO3 the center and low frequency effect (LFE) or subwoofer channels
(see
that all left channel samples are transferred first including the center channel, followed by
all right channel samples including the LFE channel.
In 16-bit operation, sample pairs are packed with the right samples occupying the upper
halfword and left samples the lower halfword of the FIFO entries.
For 17-bit to 24-bit operation, sample pairs are placed in individual FIFO entries, left channel
first then followed by the right channel, and are right justified (LSB in bit 0) in each FIFO
entry.
The FIFO underflow, overflow, and service interrupt status bits reside within the
HW_SAIF_STAT register.
35.2.6 Serial Frame Formats
There are six types of serial PCM frames that can be transmitted or received. The three
basic formats are I
a frame based on whether or not the data consumes the entire frame width, these three
formats have two frame types each that make up the six basic frame types. One variation
exists for 16-bit and 24-bit serial PCM data that consumes the whole frame width, and the
other for 17-bit to 24-bit serial PCM data that does not. Recall that for 16-bit operation,
BITCLK is either 32xFs or 48xFs, while for 17-bit to 24-bit, it is either 48xFs or 64xFs.
These six types of serial PCM frames are shown in
For both LJ and RJ formats, LRCLK is high for left samples and low for right samples. For
I
2210
2
S, it is the opposite: LRCLK is low for left samples and high for right samples.
• In left-justified (LJ) format, the serial PCM data is left-justified within the sample's
• Conversely, in right-justified (RJ) format, the last bit of PCM data in a sample is
• I
start and end point indicated by the LRCLK. The first bit of PCM data is coincident
with the first BITCLK period after LRCLK transitions.
coincident with the last BITCLK period before LRCLK transitions, indicating the start
of the next sample.
LRCLK transitions, is a null wait state, followed by the first serial PCM bit during the
next BITCLK period.
Figure
2
S format is simply a variant of LJ format, in that the first BITCLK period after the
35-1). Read/write accesses are made to the FIFOs in a round-robin fashion such
2
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
S, left-justified, and right-justified. Because there are two variations of
Figure
35-2.
Freescale Semiconductor, Inc.