MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2249

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

For general purpose, the steps are almost the same as above. The difference is the trigger
modes. The HSADC will start the conversion once triggered.
37.5 Programmable Registers
HSADC Hardware Register Format Summary
37.5.1 HSADC Control Register 0 (HW_HSADC_CTRL0)
The HSADC Control and Status Register specifies the reset state, trigger sources, and
software enable.
Freescale Semiconductor, Inc.
4. Configure the registers of APBH-DMA, write commands to external memory.
5. Configure the PWM block. The sensor needs three driving signals. Select three PWM
6. The ARM CPU keeps polling the interrupt bit of HSADC or waits for the interrupt of
8000_2000
8000_2010
8000_2020
8000_2030
8000_2040
8000_2050
8000_2060
8000_2070
8000_2080
8000_20B0
Absolute
address
(hex)
instances to generate the three driving signals with the operation clock. Select another
PWM instance to generate the trigger signals. Then start all these four PWM instances
at the same time. Then the trigger pulse generated by PWM block will start the
conversion of HSADC.
HSADC.
HSADC Control Register 0 (HW_HSADC_CTRL0)
HSADC Control Register 1 (HW_HSADC_CTRL1)
HSADC Control Register 2 (HW_HSADC_CTRL2)
HSADC Sequence Samples Number Register
(HW_HSADC_SEQUENCE_SAMPLES_NUM)
HSADC Sequence Number Register
(HW_HSADC_SEQUENCE_NUM)
HSADC FIFO Data Register (HW_HSADC_FIFO_DATA)
HSADC Debug Information 0 Register
(HW_HSADC_DBG_INFO0)
HSADC Debug Information 1 Register
(HW_HSADC_DBG_INFO1)
HSADC Debug Information 2 Register
(HW_HSADC_DBG_INFO2)
HSADC Version Register (HW_HSADC_VERSION)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Register name
HW_HSADC memory map
(in bits)
Width
32
32
32
32
32
32
32
32
32
32
Chapter 37 High-Speed ADC (HSADC)
Access
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
C000_0040h
0000_238Eh
Reset value
F000_0020h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0001_0000h
37.5.10/2260
37.5.1/2249
37.5.2/2252
37.5.3/2254
37.5.4/2256
37.5.5/2256
37.5.6/2257
37.5.7/2258
37.5.8/2259
37.5.9/2259
Section/
page
2249