MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 881

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

10.8.20 ETM Clock Control Register (HW_CLKCTRL_ETM)
This register controls the clock divider that generates the clock for the ETM, CLK_ETM.
Note: Do not write register space when busy bit(s) are high.
EXAMPLE
HW_CLKCTRL_ETM_WR(BF_CLKCTRL_ETM_DIV(4));
Address:
Freescale Semiconductor, Inc.
Reset
Reset
CLKGATE
Bit
Bit
W
W
RSRVD2
R
R
Field
12 0
Field
DIV
31
30
31
15
1
0
HW_CLKCTRL_ETM
30
14
0
0
The DIS_LCDIF clock frequency is determined by dividing the reference clock, ref_xtal or ref_pix, by the
value in this bit field. This field can be programmed with a new value only when CLKGATE = 0.
NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0. Do not divide by more than
255.
CLK_ETM Gate. If set to 1, CLK_ETM is gated off. 0: CLK_ETM is not gated. When this bit is modified, or
when it is high, the DIV field should not change its value. The DIV field can change ONLY when this clock
gate bit field is low.
Always set to zero (0).
HW_CLKCTRL_DIS_LCDIF field descriptions (continued)
BUSY
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
RSRVD1[15:8]
28
12
0
0
HW_CLKCTRL_ETM field descriptions
8004_0000h base + 130h offset = 8004_0130h
27
11
0
0
26
10
0
0
25
0
0
9
24
0
0
8
Description
Description
Chapter 10 Clock Generation and Control (CLKCTRL)
23
RSRVD1[28:16]
0
0
7
22
0
0
6
21
0
5
0
20
0
4
0
DIV
19
0
0
3
18
0
0
2
17
0
0
1
16
0
1
0
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