MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 840
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
- Current page: 840 of 2327
- Download datasheet (17Mb)
Programmable Registers
9.4.84 PINCTRL EMI Slice DS Control (HW_PINCTRL_EMI_DS_CTRL)
The PINCTRL EMI On Die Termination (DS) Control Register Controls the load and
calibration of each EMI slice.
HW_PINCTRL_EMI_DS_CTRL: 0x1b80
HW_PINCTRL_EMI_DS_CTRL_SET: 0x1b84
HW_PINCTRL_EMI_DS_CTRL_CLR: 0x1b88
HW_PINCTRL_EMI_DS_CTRL_TOG: 0x1b8C
This register controls Pad Drive Strength for the EMI SLices 0-3.
Address:
840
Reset
Reset
DDR_MODE
Bit
Bit
W
W
RSRVD1
R
R
31 18
17 16
Field
Field
31
15
RSRVD0
0
0
HW_PINCTRL_EMI_DS_CTRL 8001_8000h base + 1B80h offset = 8001_
9B80h
30
14
0
0
HW_PINCTRL_EMI_ODT_CTRL field descriptions (continued)
2= 150 ohm
3= 50 ohm
With ODT disabled:
Disabled;
Empty Description.
set working mode for EMI pads, default is DDR2 mode:
bit 1 controls DDR2_EN
ADDRESS_
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
MA
HW_PINCTRL_EMI_DS_CTRL field descriptions
28
12
0
0
CONTROL_
27
11
0
0
MA
26
10
0
0
DUALPAD_
25
RSRVD1
0
0
9
MA
24
0
0
8
Description
Description
SLICE3_MA
23
0
0
7
22
0
0
6
SLICE2_MA
21
0
5
0
20
0
4
0
Freescale Semiconductor, Inc.
SLICE1_MA
19
0
0
3
18
0
0
2
SLICE0_MA
DDR_MODE
17
1
0
1
16
1
0
0
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