MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1742

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Operation
Data is transmitted in byte format. Each data transfer has to contain eight bits. The number
of bytes transferred per transfer is unlimited. Data is transferred with the most significant
bit (MSB) first. If a receiver cannot receive another complete byte of data until it has
performed some other function, it can hold the I2C_SCL clock line low to force the
transmitter into a wait state. Data transfer can only continue when the receiver is ready for
another byte and releases the clock line.
If a slave receiver does not acknowledge the slave address (for example, it is unable to
receive because it is performing some real-time function), the data line must be left high
by the slave. The master can then abort the transfer.
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• If it is a write operation, then the software programs the DMA channel for a
• The slave search engine leaves the programmable state set up for the DMA transfer
• It then accepts eight-bit bytes and pushes them into the DMA data register,
• The DMA engine stops with the clock held and the hardware ready to acknowledge the
• If the master is requesting a read operation, then the i.MX28 slave must start sending
• After each byte, the acknowledgement from the master must be checked. When the
• If the transfer count reaches zero and the master has not sent an MNAK or stop condition,
DMA_WRITE (to on-chip RAM or off-chip SDRAM).
engine to send the address acknowledge for the address byte as soon as the clock is
released.
acknowledging each data byte as it is received, until the transfer count reaches zero.
last byte when the clock is released. Software decides whether the last byte is
acknowledged or not.
data on the I2C_SDA bus immediately after acknowledging the slave address and RW
bit.
master has received the last byte, it does not send an acknowledgement, and the slave
terminates while setting the Early Termination interrupt request. This notifies software
that the DMA will not be interrupting for the termination and that software should deal
with a shorter than expected packet of data.
then the slave DMA transfer controller terminates the transfer while setting the Oversize
Transfer interrupt request. This notifies software to set up for an additional buffer of
data to transmit to the master.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.