MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1550

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Overview
25.2 Overview
The CAN protocol was primarily, but not only, designed to be used as a vehicle serial data
bus, meeting the specific requirements of this field: real-time processing, reliable operation
in the EMI environment of a vehicle, cost-effectiveness and required bandwidth. The
FlexCAN module is a full implementation of the CAN protocol specification, Version 2.0
B, which supports both standard and extended message frames. The Message Buffers are
stored in an embedded RAM dedicated to the FlexCAN module.
The CAN Protocol Interface (CPI) sub-module manages the serial communication on the
CAN bus, requesting RAM access for receiving and transmitting message frames, validating
received messages and performing error handling. The Message Buffer Management (MBM)
sub-module handles Message Buffer selection for reception and transmission, taking care
of arbitration and ID matching algorithms. The Bus Interface Unit (BIU) sub-module controls
the access to and from the internal interface bus, in order to establish connection to the CPU
and other blocks. Clocks, address and data buses, interrupt outputs and test signals are
accessed through the Bus Interface Unit, which is compliant to APB Bus Specification.
25.2.1 Features
The FlexCAN module includes the following distinctive Features:
1550
• Full Implementation of the CAN protocol specification, Version 2.0B
• 64 Message Buffers of zero to eight bytes data length
• Each MB configurable as Rx or Tx, all supporting standard and extended messages
• Individual Rx Mask Registers per Message Buffer
• Includes either 1056 bytes (64 MBs) of RAM used for MB storage
• Includes either 256 bytes (64 MBs) of RAM used for individual Rx Mask Registers
• Full featured Rx FIFO with storage capacity for six frames and internal pointer handling
• Standard data and remote frames
• Extended data and remote frames
• Zero to eight bytes data length
• Programmable bit rate up to 1 Mb/sec
• Content-related addressing
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.