MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1834

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Output Frame Queuing
29.5.5.2 Weighted Fair Queuing scheduling algorithm
The weight of each queue, common for all ports, can be configured between 0 and 30 with
the register QM_WEIGHTS. A Queue with a higher weight is served more often than a
queue with lower weight.
Queue 0 represents the lowest priority, Queue 3 the highest priority queue.
The scheduler first serves the queue with the highest weight. Each time the scheduler serves
a queue, the weight of the other queues is increased and the weight of the selected queue is
reset (decreased) to its programmed weight value. This guarantees that all queues are served
eventually.
When multiple queues have the same weight, the queue with the higher number is served
first.
If all weights are programmed to 0 (default), a strict priority scheme is active where the
higher priority queues are served as long as they are not empty.
29.5.6 Congestion Management
The Write control logic is protected against memory overflow. When data is written is the
cell factory has no more free cells (Number of available cells less than value programmed
in register
QMGR_MINCELLS
), the frame is discarded or terminated with an error (i.e.
forwarded to the output queue manager with the end-of-packet and error indication).
If the congestion persists, the Switch resolves the congestion as specified in section
"Congestion Resolution".
29.5.7 Implementation Notes
Memory Size
The memory controller is capable of addressing up to 32768 bytes of memory. The external
address bus to the shared memory provides the necessary bits to address a memory of size
8192x32 (deep x wide).
However, only 24 Kbyte will be used and the controller will only use addresses from 0 to
6143.
Datapath
The switch and all datapath has a width of 32 bit.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
1834
Freescale Semiconductor, Inc.