MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 850
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MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
- Current page: 850 of 2327
- Download datasheet (17Mb)
CLKCTRL Digital Clock Divider
These modes are described in the following three sections.
10.3.1 Integer Clock Divide Mode
Each divider has the capability to divide an input reference frequency by a fixed integer
value. This is the most common mode that will be used to select a particular clock frequency.
For a desired clock frequency, first try to select a PFD reference clock frequency AND an
integer clock divide value to achieve the desired clock domain frequency. This mode is
selected when the respective frac_en field in the clock control register is logic 0. The divide
value will be in the range of 1 to 2^N. When programming the DIV field to 1, the reference
clock for the domain is passed and the clock domain assumes the same frequency as the
reference domain. When a value of 2 is programmed, the clock domain frequency will be
half the reference clock frequency. The maximum divide value depends on the number of
bits each digital clock divider implements. This is different for each digital clock divider.
The number of bits implemented for each divider is indicated by each DIV field that controls
each clock domain. Divide by zero is NOT a valid programming value for the DIV field of
any clock control PIO register.
10.3.2 Fractional Clock Divide Mode
This mode is used to divide a reference clock in the range of 2 < div < 2^N. The fractional
clock divider in the CLKCTRL module implements a fractional counter to approximate a
divided clock with respect to the selected reference frequency. The accuracy of the output
clock is dependent on the extent of the bits used to implement the fractional counter. The
reference clock frequency and the fractional divide value must both be selected to achieve
the desired output frequency.
This mode is enabled when setting the FRAC_EN field of the respective clock domain
control register to logic 1 AND the most significant bit of the DIV field is logic 0. Do NOT
use this mode to divide the reference clock domain by an integer value (such as 4, 8, and
so on). Use the integer divide mode to achieve the best results to divide by an integer.
850
• Fractional divide mode
• Gated clock divide mode
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.
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