MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2206

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Operation
while in slave clock mode it is the responsibility of the codec to drive BITCLK and LRCLK
to the SAIF. Note that, for any of these modes, an alternate MCLK reference can be
multiplexed out to a pin to drive the codec's main system clock.
In slave clocking mode, the SAIF configures the BITCLK and LRCLK pins as inputs, and
the off-chip codec is responsible for driving both clocks to the SAIF. The SAIF synchronizes
these inputs and uses them to determine when to latch serial PCM data from the ADC for
receive. The codec must be configured to run BITCLK either at 32xFs for 16-bit operation,
64xFs for 17-bit through 24-bit operation, or 48xFs for certain codecs for 16-bit through
24-bit operation.
In master clocking mode, it is the responsibility of the SAIF to drive both BITCLK and
LRCLK out to the off-chip codec. In this mode, BITCLK is again programmed to transition
at a the standard 32x, 48x, or 64x the sample rate.
On the device, two SAIF modules are instantiated on-chip. Each SAIF has a set of clock
pins and can be operating in master mode simultaneously if they are connected to different
off-chip codecs. Also, one of the two SAIFs can master or drive the clock pins while the
other SAIF, in slave mode, receives clocking from the master SAIF. This also means that
both SAIFs must operate at the same sample rate. Following are the valid configurations
for SAIF1 and SAIF2 on the i.MX28:
For any of these configurations, MCLK can also be output through a multiplexed pin to
provide the clock reference for the off-chip codec.
Configuring the SAIF for transmit makes it the master by default. However, for receive,
the SAIF can either be master or slave. For master mode, it drives BITCLK and LRCLK
to the pins the off-chip codec, which uses the clocks to time when to serially transmit PCM
data back to the SAIF. For slave mode, the BITCLK and LRCLK are pin inputs driven by
the off-chip codec or the other SAIF (master), and the SAIF (slave) uses these clocks to
determine when to latch each incoming bit and push the assembled PCM data to the FIFO.
2206
• One SAIF in TX mode (is the default clock master) while the other SAIF is in RX slave
• One SAIF in RX master mode while the other SAIF is in RX slave mode and again is
• Both SAIFs in RX slave mode, with BITCLK and LRCLK controlled by the off-chip
• Both SAIFs in master mode, driving their BITCLK and LRCLK.
• Only one SAIF used (any configuration).
mode and is internally controlled by the TX SAIF's BITCLK and LRCLK.
internally controlled by the RX master SAIF's BITCLK and LRCLK.
codec.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.