MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1326

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

SD/SDIO/MMC Mode
To boost the performance of SSP running in DDR mode and at the maximum frequency,
the DMA interface allows a burst of 4 or 8 32-bit APB transfers per DMA request.
17.8.2.3 SD/MMC Block Transfer CRC Protection
The block of data transferred over the data bus is protected by CRC16. For reads, the SSP
calculates the CRC of the incoming data and compares it to the CRC16 reference that is
provided by the card at the end of the block. In DDR mode, two sets of CRC16s are
calculated for both the rising edge sampled data and the falling edge sampled data. If any
CRC mismatch occurs, then the block asserts the DATA_CRC_ERR status flag. If
DATA_CRC_IRQ_EN is set, then a CPU IRQ is asserted.
For block write operations, the card determines if a CRC error has occurred. After the SSP
has sent a block of data, it transmits the reference CRC16. In DDR mode, two sets of
reference CRC16s are transmitted. The card compares that(those) to its calculated CRC16(s).
The card then sends a CRC status token on the DATA bus. It sends a positive status ('010')
if the transfer was good, and a negative status ('101') if the CRC16(s) did not match. If the
SSP receives a CRC bad token, it sets the DATA_CRC_ERROR in the HW_SSP_STATUS
register, and then it indicates it to the CPU if DATA_CRC_IRQ_EN is set.
17.8.3 eMMC Boot Operation
In boot operation mode, the SSP can read boot data from the slave (MMC device) by keeping
SSP_CMD line low using PRIM_BOOT_OP_EN bit, or sending CMD0 with argument =
0xFFFFFFFA, before issuing CMD1. User can terminate the boot operation by setting
SOFT_TERMINATE bit in HW_SSP_CMD0 register when using primary boot method,
or send a CMD0 command when using the alternate boot method. Boot acknowledge is
also supported by setting BOOT_ACK_EN bit in HW_SSP_CMD0 register. The boot mode
supports DDR operations as specified in eMMC 4.4 standard.
1326
• To set TXCLK_DELAY_TYPE of HW_SSP_DDR_CTRL register allows SCK to
• Turn on the DLL by setting ENABLE bit of HW_SSP_DLL_CTRL registerr. This
have a 1/4 SCK delay and to switch approximately at the center of each TX DATA
period.
generates a precisive clock delay relative to SCK (input version), which is used to
sample RX DATA. Program the value of 4'd7 to DLV_DLY_TARGET field of
HW_SSP_DLL_CTRL register, and this specifies the clock delay to be 1/4 of SCK
period.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.