MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1541

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

24.3.9 UART Interrupt FIFO Level Select Register (HW_UARTDBG_IFLS)
The IFLS register is the Interrupt FIFO Level Select Register. You can use the IFLS register
to define the FIFO level at which the UARTTXINTR and UARTRXINTR are triggered.
The interrupts are generated based on a transition through a level rather than being based
on the level. That is, the design is such that the interrupts are generated when the fill level
progresses through the trigger level. The bits are reset so that the trigger level is when the
FIFOs are at the half-way mark.
Address:
Re-
Freescale Semiconductor, Inc.
set
Bit
W
R
UNAVAILABLE
RXIFLSEL
TXIFLSEL
Reserved
31
UARTEN
0
SIREN
31 16
Field
Field
15 6
5 3
2 0
30
1
0
0
29
0
HW_UARTDBG_IFLS
28
0
SIR Enable. Not Supported.
UART Enable. If this bit is set to 1, the UART is enabled. Data transmission and reception occurs for the
UART signals. When the UART is disabled in the middle of transmission or reception, it completes the current
character before stopping.
The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are
always unavailable.
This bitfield is reserved.
Reserved, do not modify, read as zero.
Receive Interrupt FIFO Level Select. The trigger points for the receive interrupt are as follows:
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Transmit Interrupt FIFO Level Select. The trigger points for the transmit interrupt are as follows:
0x0
0x1
27
0
26
0
ONE_EIGHT — Trigger when FIFO becomes at least one-eight full.
ONE_QUARTER — Trigger when FIFO becomes at least one-quarter full.
ONE_HALF — Trigger when FIFO becomes at least one-half full.
THREE_QUARTERS — Trigger when FIFO becomes at least three-quarters full.
SEVEN_EIGHTHS — Trigger when FIFO becomes at least seven-eights full.
INVALID5 — Reserved.
INVALID6 — Reserved.
INVALID7 — Reserved.
ONE_EIGHT — Trigger when FIFO becomes equal or less than one-eight full.
ONE_QUARTER — Trigger when FIFO becomes equal or less than one-quarter full.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
UNAVAILABLE
25
HW_UARTDBG_CR field descriptions (continued)
0
24
0
23
HW_UARTDBG_IFLS field descriptions
0
22
0
8007_4000h base + 34h offset = 8007_4034h
21
0
20
0
19
0
18
0
17
0
16
0
15
0
Description
Description
14
0
13
0
12
0
RESERVED
11
0
10
0
0
9
Chapter 24 Debug UART (DUART)
0
8
0
7
0
6
RXIFLSEL
0
5
1
4
3
0
TXIFLSEL
0
2
1
1
1541
0
0