MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1098

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

DDR PHY
14.7.4 Data Slice Overview
Each data-slice manages a byte (8-bit) of data and it’s corresponding signals.
The Read Data Path captures read data by latching it into read data buffers by both the
posedge and negedge of delayed_dqs. Then, the read data is synchronized from delayed_dqs
clock domain to emi_clk domain.
The Write Data Path synchronizes write data and write data mask (the dm) from emi_clk
domain to the dqs_out domain.
The Digital DLL controls the delay values of read delay-line and write delay-line. It can be
bypassed and switched to manual delay control mode. In manual delay control mode, the
delay values of read/write delay-line can be programmed separately into the control registers.
1098
EMI_CLK
write
read
data
data
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Read Delay-Line
Write Delay-Line
Read Data
Figure 14-9. DDR PHY Data Slice
Delay Control
Digital DLL &
I/O Control
delayed_dqs
Path
Write Data
Path
Data Slice
(delayed)
clk_wr
io_dq_out [7:0]
io_dq_oe [7:0]
io_dq_in [7:0]
io_dqs_out
io_tsel_dm
io_dqs_oe
io_dm_oe
io_dqs_in
io_tsel
io_dm
Freescale Semiconductor, Inc.