MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1062

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

EMI Address Mapping
EMI implements the following five bus interfaces:
14.2 EMI Address Mapping
The EMI automatically maps AXI and AHB bus addresses to the DRAM memory in a
contiguous block. Addressing starts at user address 0 and ends at the highest available
address according to the size and number of DRAM devices present. This mapping is
dependent on how the memory controller was configured and how the parameters in the
internal EMI registers are programmed. The exact number and values of these parameters
depends on the configuration and the type of memory for which the memory controller was
designed.
The mapping of the address space to the internal data storage structure of the DRAM devices
is based on the actual size of the DRAM devices available. The size is stored in
user-programmable parameters that must be initialized at power up. Certain DRAM devices
allow for different mapping options to be chosen, while other DRAM devices depend on
the burst length chosen.
1062
• One 64-bit AXI bus interface
• Three 32-bit AHB bus interfaces to read or write data from or to external DDR memory
• One AHB interface dedicated to read/write PIO registers
AHB - 32
AHB - 32
AHB - 32
AHB - 32
AXI - 64
AHB-2-AXI
AHB-2-AXI
AHB-2-AXI
Register Port
Bridge
Bridge
Bridge
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
AHB
Figure 14-1. EMI Top-Level Block Diagram
Interface
Interface
Interface
Interface
AXI
AXI
AXI
AXI
Programmable Register Settings
Read/Write
Read/Write
Command
E M I
Queues
Queue
Arbiter
Data
Bus
&
&
Control
Logic
DDR
DFI
DDR
PHY
Freescale Semiconductor, Inc.
DDR Memory
External