MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1026

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
Address:
1026
Reset
Reset
PRESENT_SHA
RESIDUAL_
CONTEXT_
PRESENT_
CLKGATE
GATHER_
CACHING
Bit
Bit
ENABLE_
W
W
CRYPTO
SFTRST
WRITES
R
R
RSVD1
27 24
Field
31
30
29
28
23
22
31
15
1
0
HW_DCP_CTRL
30
14
1
0
Set this bit to zero to enable normal DCP operation. Set this bit to one (default) to disable clocking with the
DCP and hold it in its reset (lowest power) state. This bit can be turned on and then off to reset the DCP
block to its default state.
This bit must be set to zero for normal operation. When set to one it gates off the clocks to the block.
Indicates whether the crypto (Cipher/Hash) functions are present.
0x1
0x0
Indicates whether the SHA1/SHA2 functions are present.
0x1
0x0
Reserved, always set to zero.
Software should set this bit to enable ragged writes to unaligned buffers to be gathered between multiple
write operations. This improves performance by removing several byte operations between write bursts.
Trailing byte writes are held in a residual write data buffer and combined with a subsequent write to the
buffer to form a word write.
Software should set this bit to enable caching of contexts between operations. If only a single channel is
used for encryption/hashing, enabling caching causes the context to not be reloaded if the channel was the
last to be used.
29
13
1
0
Present —
Absent —
Present —
Absent —
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
RSVD0[15:9]
28
12
1
0
8002_8000h base + 0h offset = 8002_8000h
HW_DCP_CTRL field descriptions
27
11
0
0
26
10
0
0
RSVD1
25
0
0
9
24
0
0
8
Description
23
1
0
7
22
0
0
6
CHANNEL_INTERRUPT_ENABLE
21
0
5
0
20
0
4
0
Freescale Semiconductor, Inc.
19
0
0
3
RSVD0[20:16]
18
0
0
2
17
0
0
1
16
0
0
0