MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2245

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

37.3.3 Bits Location
The original output sample data is 12-bits. The user can configure the
ADC_SAMPLE_PRECISION bits in HSADC Control Register 0 to determine the bits used
for one sample. When 8-bits mode is selected, four sample data will be put in one word as
Figure 37-6
word as
in one word as
bit15-bit13 are used for storing the channel number from which this sample is captured.
Then the software can sort the data in external memory and store to different memory space
by the channel number. This feature is useful when there are channels switching for capturing
the samples from many channels.
37.3.4 Configuration of APBH-DMA
There is one APBH-DMA channel connected to HSADC. Once there is sample data written
into the asynchronous FIFO inside the high-speed ADC block, the high-speed ADC block
will assert the dma_req, then the DMA will read the sample data through the APBH bus
and then write to the external memory. When the user case is to drive a linear image scanner
sensor, it is suggested to use one DMA command to transfer one sequence of sample data.
And when one sequence is finished, the high-speed ADC block will assert dma_end so that
the DMA can switch to the next command. The dma_run can also start the high-speed ADC
block. So when dma_run is asserted, the high-speed ADC block will enter into the status
to wait for the trigger pulse.
Freescale Semiconductor, Inc.
Figure 37-7
indicate. When 10-bits mode is selected, two sample data will be put in one
Figure 37-8
Figure 37-7. Bits Location Of Sample Data In 10-bits Mode
Figure 37-6. Bits Location Of Sample Data In 8-bits Mode
Figure 37-8. bits location of sample data in 12-bits mode
Bit 31
Bit 31 Bit 30
Bit 31
Channel number
Channel number
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Bit 30
Bit 30
Bit 29
Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22
Bit 29
indicate. When 12-bits mode is selected, two sample data will be put
Sample data 3
Bit 28
Bit 28
Bit 27
Bit 27
Bit 26
Bit 26
indicate. In 10-bits mode and 12-bits mode, the bit31-bit29 and
Bit 25
Bit 25
Bit 24
Bit 24
Bit 23
Bit 23
Sample data 1
Bit 22
Bit 22
Sample data 1
Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Bit 21
Bit 21
Sample data 2
Bit 20
Bit 20
Bit 19
Bit 19
Bit 18
Bit 18
Bit 17
Bit 17
Bit 16
Bit 16
Bit 15
Bit 15
Channel number
Channel number
Bit 14
Bit 14
Bit 13
Bit 13
Sample data 1
Bit 12
Bit 12
Bit 11
Bit 11
Bit 10
Bit 10
Bit 9
Bit 9
Bit 9
Bit 8
Bit 8
Bit 8
Bit 7
Bit 7
Bit 7
Chapter 37 High-Speed ADC (HSADC)
Sample data 0
Bit 6
Bit 6
Bit 6
Bit 5
Bit 5
Sample data 0
Bit 5
Sample data 0
Bit 4
Bit 4
Bit 4
Bit 3
Bit 3
Bit 3
Bit 2
Bit 2
Bit 2
Bit 1
Bit 1
Bit 1
Bit 0
Bit 0
Bit 0
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