MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1551

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

25.2.2 Modes of Operation
The FlexCAN module has four functional modes: Normal Mode, Freeze Mode, Listen-Only
Mode and Loop-Back Mode. There are also two low power modes: Disable Mode, Stop
Mode.
Freescale Semiconductor, Inc.
• Powerful Rx FIFO ID filtering, capable of matching incoming IDs against either 8
• Selectable backward compatibility with previous FlexCAN version
• CAN Protocol Interface with clock only from crystal oscillator
• Unused MB and Rx Mask Register space can be used as general purpose RAM space
• Listen only mode capability
• Programmable loop-back mode supporting self-test operation
• Programmable transmission priority scheme: lowest ID, lowest buffer number or highest
• Time Stamp based on 16-bit free-running timer
• Global network time, synchronized by a specific message
• Maskable interrupts
• Independent of the transmission medium (an external transceiver is assumed)
• Short latency time due to an arbitration scheme for high-priority messages
• Low power modes, with programmable wake up on bus activity
• Configurable Glitch filter width to filter the noise on CAN bus when waking up
• Normal Mode :
• Freeze Mode:
extended, 16 standard or 32 partial (8 bits) IDs, with individual masking capability
priority
In Normal Mode, the module operates receiving and/or transmitting message frames,
errors are handled normally and all the CAN Protocol functions are enabled.
It is enabled when the FRZ bit in the MCR Register is asserted. If enabled, Freeze Mode
is entered when the HALT bit in MCR is set or when Debug Mode is requested. In this
mode, no transmission or reception of frames is done and synchronicity to the CAN
bus is lost. See
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freeze Mode
for more information.
Chapter 25 Controller Area Network (FlexCAN)
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