MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1575

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Chapter 25 Controller Area Network (FlexCAN)
The sensitivity to CAN bus activity can be modified by applying a low-pass filter function
to the Rx CAN input line while in Stop Mode. This feature can be used to protect FlexCAN
from waking up due to short glitches on the CAN bus lines. Such glitches can result from
electromagnetic interference within noisy environments.
25.4.11.4 Interrupts
The module can generate up to 70 interrupt sources (64 interrupts due to message buffers
and 6 interrupts due to ORed interrupts from MBs, Bus Off, Error, Tx Warning, Rx Warning
and Wake Up).
Each one of the message buffers can be an interrupt source, if its corresponding IMASK
bit is set. There is no distinction between Tx and Rx interrupts for a particular buffer, under
the assumption that the buffer is initialized for either transmission or reception. Each of the
buffers has assigned a flag bit in the IFLAG Registers. The bit is set when the corresponding
buffer completes a successful transmission/reception and is cleared when the ARM writes
it to 1 (unless another interrupt is generated at the same time).
If the Rx FIFO is enabled (bit FEN on MCR set), the interrupts corresponding to MBs 0 to
7 have a different behavior. Bit 7 of the IFLAG1 becomes the FIFO Overflow flag; bit 6
becomes the FIFO Warning flag, bit 5 becomes the Frames Available in FIFO flag and bits
4-0 are unused.
A combined interrupt for all MBs is also generated by an OR of all the interrupt sources
from MBs. This interrupt gets generated when any of the MBs generates an interrupt. In
this case the ARM must read the IFLAG Registers to determine which MB caused the
interrupt.
The other 5 interrupt sources (Bus Off, Error, Tx Warning, Rx Warning and Wake Up)
generate interrupts like the MB ones, and can be read from the Error and Status Register.
The Bus Off, Error, Tx Warning and Rx Warning interrupt mask bits are located in the
Control Register, and the Wake-Up interrupt mask bit is located in the MCR.
25.5 Initialization/Application Information
This section provide instructions for initializing the FlexCAN module.
25.5.1 FlexCAN Initialization Sequence
The FlexCAN module may be reset in three ways:
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.
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