MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2058

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Operation
that assists data crossing between the two clock domains. In the read datapath, there is a
16-deep asynchronous RXFIFO that is read by DMA operation. The following sub-sections
describe the two system bus interface mechanisms.
33.2.1.1 Bus Master Operation in Write/Display Modes
In this mode, the LCDIF block acts as a master on AXI fabric shared with other blocks like
PXP. This is a high performance mode and does not require DMA descriptor setup. The
LCDIF_MASTER bit must be set to 1 to enable bus master operations. Software should
program the
CUR_BUF
and
NEXT_BUF
registers to point to the base of the frame buffers
that needs to be transferred out. In the MPU and VSYNC modes, once the frame buffer
pointed to by the HW_LCDIF_CUR_BUF_ADDR is transferred out, LCDIF stops
transmitting and turns off the RUN bit in
CTRL
register. It has to be setup and kicked off
again for transmitting the next frame. In the DOTCLK and DVI modes, which are streaming
modes in the true sense, software should start off with programming both the
HW_LCDIF_CUR_BUF_ADDR and HW_LCDIF_NEXT_BUF_ADDR registers, and
then, it only has to update the HW_LCDIF_NEXT_BUF_ADDR register in every frame.
LCDIF will automatically update the HW_LCDIF_CUR_BUF_ADDR register with the
value in HW_LCDIF_NEXT_BUF_ADDR at the end of current frame and start fetching
the next frame from the new address. Thus, software has about one frame worth of time to
update HW_LCDIF_NEXT_BUF_ADDR before it actually gets used. If for some reason,
the HW_LCDIF_NEXT_BUF_ADDR register was not updated within a frame, LCDIF will
keep transmitting the last frame until a new value is programmed into that register. The
performance of the LCDIF block can be tweaked by changing the burst length and the
number of outstanding requests that can be issued at a time depending on the bandwidth
requirements.
LCDIF also provides the capability of interlacing a progressive frame by fetching odd lines
in the first field and then fetching even lines in the second field. This feature can be used
in the DVI mode and can be turned on by setting the INTERLACE_FIELDS bit in the
HW_LCDIF_CTRL1 register.
33.2.1.2 DMA Operation in MPU Read Mode
Unlike previous generation SoCs, the DMA operation is now only used with the MPU read
mode. None of the write modes can use the DMA for display purposes since APBH DMA
will not be able to keep up with the high bandwidth requirements of the i.MX28. The LCDIF
block resides on the AHB-APBH bridge DMA as a DMA slave. The AHB-APBH bridge
DMA is used to move data from an external LCD controller, or any device that uses a
6800/8080 type interface, that needs to send data to the CPU through the LCDIF block. The
software designer can take advantage of the DMA's linked descriptors that give substantial
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
2058
Freescale Semiconductor, Inc.