MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2277

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

38.5.3 LRADC Control Register 2 (HW_LRADC_CTRL2)
The LRADC Control Register 2 provides overall control of the eight low resolution analog
to digital converters.
Freescale Semiconductor, Inc.
LRADC6_IRQ
LRADC5_IRQ
LRADC4_IRQ
LRADC3_IRQ
LRADC2_IRQ
LRADC1_IRQ
LRADC0_IRQ
Field
6
5
4
3
2
1
0
0x0
0x1
This bit is set to one upon completion of a scheduled conversion for channel 6. It is ANDed with its
corresponding interrupt enable bit to request an interrrupt. Once set by the conversion hardware, this bit
remains set until cleared by software.
0x0
0x1
This bit is set to one upon completion of a scheduled conversion for channel 5. It is ANDed with its
corresponding interrupt enable bit to request an interrrupt. Once set by the conversion hardware, this bit
remains set until cleared by software.
0x0
0x1
This bit is set to one upon completion of a scheduled conversion for channel 4. It is ANDed with its
corresponding interrupt enable bit to request an interrrupt. Once set by the conversion hardware, this bit
remains set until cleared by software.
0x0
0x1
This bit is set to one upon completion of a scheduled conversion for channel 3. It is ANDed with its
corresponding interrupt enable bit to request an interrrupt. Once set by the conversion hardware, this bit
remains set until cleared by software.
0x0
0x1
This bit is set to one upon completion of a scheduled conversion for channel 2. It is ANDed with its
corresponding interrupt enable bit to request an interrrupt. Once set by the conversion hardware, this bit
remains set until cleared by software.
0x0
0x1
This bit is set to one upon completion of a scheduled conversion for channel 1. It is ANDed with its
corresponding interrupt enable bit to request an interrrupt. Once set by the conversion hardware, this bit
remains set until cleared by software.
0x0
0x1
This bit is set to one upon completion of a scheduled conversion for channel 0. It is ANDed with its
corresponding interrupt enable bit to request an interrrupt. Once set by the conversion hardware, this bit
remains set until cleared by software.
0x0
0x1
CLEAR — Interrupt request cleared.
PENDING — Interrupt request pending.
CLEAR — Interrupt request cleared.
PENDING — Interrupt request pending.
CLEAR — Interrupt request cleared.
PENDING — Interrupt request pending.
CLEAR — Interrupt request cleared.
PENDING — Interrupt request pending.
CLEAR — Interrupt request cleared.
PENDING — Interrupt request pending.
CLEAR — Interrupt request cleared.
PENDING — Interrupt request pending.
CLEAR — Interrupt request cleared.
PENDING — Interrupt request pending.
CLEAR — Interrupt request cleared.
PENDING — Interrupt request pending.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_LRADC_CTRL1 field descriptions (continued)
Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface
Description
2277