MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2215

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Freescale Semiconductor, Inc.
WORD_LENGTH
BITCLK_48XFS_
BITCLK_EDGE
SLAVE_MODE
POLARITY
JUSTIFY
ENABLE
LRCLK_
Field
7 4
10
9
8
3
2
0 = Data is not delayed. MSB of serial sample is output/input coincident with LRCLK transition (left-justified
mode)
1 = Data is delayed one BITCLK period. MSB of serial serial sample is output/input one BITCLK period after
LRCLK transitions (I2S mode).
Note that this bit is ignored in right-justified mode (JUSTIFY=1).
SAIF Data Justification. This bit selects whether serial PCM data is left- or right-justified within each sample's
LRCLK frame.
0 = Data is left-justified (start or MSB of serial sample transmission/reception coincides with LRCLK transition)
1 = Data is right-justified (end or LSB of serial sample transmission/reception coincides with LRCLK transition).
SAIF LRCLK Polarity Select. This bit selects which LRCLK levels (high/low) correspond to left and right
PCM samples.
0 = Left low/right high
1 = Left high/right low.
SAIF BITCLK Edge Select. For both transmit and receive, this bit selects the BITCLK edge upon which serial
PCM data changes. For receive, data is sampled and stored to the receive FIFO on the opposite edge as
selected by BITCLK_EDGE that corresponds to the midpoint of the data.
0 = TX: data is driven (changes) on falling-edges of BITCLK; RX: data is sampled on rising-edges of BITCLK
1 = TX: data is driven (changes) on rising-edges of BITCLK; RX: data is sampled on falling-edges of BITCLK.
SAIF data size. Selects one of nine PCM data widths from 16-bit to 24-bit to serially input or output from/to
a codec. 17-bit to 24-bit PCM data should be right-justified (LSB in bit 0) when it is DMAed or written to the
HW_SAIF_DATA register. These samples should be interleaved starting with a left sample first, followed
by a right, then left and so on. For 16-bit PCM data, stereo pairs should be constructed with the right sample
in the upper half-word (bits 31-16) and the left sample in the lower half word (bits 15-0).
0000 = 16-bit
0001 = 17-bit
0010 = 18-bit
0011 = 19-bit
0100 = 20-bit
0101 = 21-bit
0110 = 22-bit
0111 = 23-bit
1000 = 24-bit
1001-1111 = Reserved but defaults to 24-bit.
BITCLK 48x Sample Rate Enable. For 384x base frequency multiples, this bit enables generation of 48
BITCLKs per sample pair (24 BITCLKs per channel or LRCLK transition) when the SAIF is BITCLK master.
This bit is ignored for the following cases: BITCLK_BASE_RATE=0, or READ_MODE=1, or READ_MODE=0
and SLAVE_MODE=1.
SAIF Receive Master/Slave Clock Mode Select. For receive operation, this bit selects whether BITCLK and
LRCLK are driven to the off-chip codec or uses the two clock pins as inputs to determine when to receive
data from the codec. In receive master mode (SLAVE_MODE=0), BITCLK and LRCLK are output to the
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_SAIF_CTRL field descriptions (continued)
Description
Chapter 35 Serial Audio Interface (SAIF)
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