MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2152

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
34.4.2 PXP Status Register (HW_PXP_STAT)
The PXP Interrupt Status register provides interrupt status information.
HW_PXP_STAT: 0x010
HW_PXP_STAT_SET: 0x014
HW_PXP_STAT_CLR: 0x018
2152
IRQ_ENABLE
NEXT_IRQ_
OUTBUF_
Reserved
FORMAT
ENABLE
ENABLE
ROTATE
Field
9 8
7 4
3
2
1
0
Indicates the clockwise rotation to be applied at the output buffer. The rotation effect is defined as occurring
after the FLIP_X and FLIP_Y permutation.
0x0
0x1
0x2
0x3
Output framebuffer format. The UV byte lanes are synonymous with CbCr byte lanes for YUV output pixel
formats. For example, the YUV2P420 format should be selected when the output is YCbCr 2-plane 420
output format.
0x0
0x1
0x2
0x3
0x4
0x5
0x7
0xA
0xB
0xC
0xD
0xE
0xF
This bit is reserved.
Reserved, always set to zero.
Next command interrupt enable. When set, the PXP will issue an interrupt when a queued command initiated
by a write to the PXP_NEXT register has been loaded into the PXP's registers. This interrupt also indicates
that a new command may now be queued.
Interrupt enable. NOTE: When using the HW_PXP_NEXT functionality to reprogram the PXP, the new value
of this bit will be used and may therefore enable or disable an interrupt unintentionally.
Enables PXP operation with specified parameters. The ENABLE bit will remain set while the PXP is active
and will be cleared once the current operation completes. Software should use the IRQ bit in the
HW_PXP_STAT when polling for PXP completion.
ROT_0 —
ROT_90 —
ROT_180 —
ROT_270 —
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
ARGB8888 — 32-bit pixels
RGB888 — 32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.)
RGB888P — 24-bit pixels (packed 24-bit format)
ARGB1555 — 16-bit pixels
RGB565 — 16-bit pixels
RGB555 — 16-bit pixels
YUV444 — 32-bit pixels (1-plane XYUV unpacked)
UYVY1P422 — 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
VYUY1P422 — 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
YUV2P422 — 16-bit pixels (2-plane UV interleaved bytes)
YUV2P420 — 16-bit pixels (2-plane UV)
YVU2P422 — 16-bit pixels (2-plane VU interleaved bytes)
YVU2P420 — 16-bit pixels (2-plane VU)
HW_PXP_CTRL field descriptions (continued)
Description
Freescale Semiconductor, Inc.