MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1024
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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- Download datasheet (17Mb)
Programmable Registers
</code>
13.3 Programmable Registers
DCP Hardware Register Format Summary
1024
8002_80C0
8002_80D0
8002_8000
8002_8010
8002_8020
8002_8030
8002_8040
8002_8050
8002_8060
8002_8070
8002_8080
8002_8090
8002_80A0
8002_80B0
8002_80E0
8002_8100
8002_8110
8002_8120
8002_8130
8002_8140
8002_8150
// polling code
while ( (HW_DCP_STAT_RD() & 0x01) == 0x00 );
// now check/clear channel status
if ( (HW_DCP_CHnSTAT_RD(0) & 0xFF) != 0 ) {
}
// clear interrupt register
HW_DCP_STAT_CLR(1);
Absolute
address
(hex)
// an error occurred
HW_DCP_CHnSTAT_CLR(0, 0xff);
DCP Control Register 0 (HW_DCP_CTRL)
DCP Status Register (HW_DCP_STAT)
DCP Channel Control Register (HW_DCP_CHANNELCTRL)
DCP Capability 0 Register (HW_DCP_CAPABILITY0)
DCP Capability 1 Register (HW_DCP_CAPABILITY1)
DCP Context Buffer Pointer (HW_DCP_CONTEXT)
DCP Key Index (HW_DCP_KEY)
DCP Key Data (HW_DCP_KEYDATA)
DCP Work Packet 0 Status Register (HW_DCP_PACKET0)
DCP Work Packet 1 Status Register (HW_DCP_PACKET1)
DCP Work Packet 2 Status Register (HW_DCP_PACKET2)
DCP Work Packet 3 Status Register (HW_DCP_PACKET3)
DCP Work Packet 4 Status Register (HW_DCP_PACKET4)
DCP Work Packet 5 Status Register (HW_DCP_PACKET5)
DCP Work Packet 6 Status Register (HW_DCP_PACKET6)
DCP Channel 0 Command Pointer Address Register
(HW_DCP_CH0CMDPTR)
DCP Channel 0 Semaphore Register (HW_DCP_CH0SEMA)
DCP Channel 0 Status Register (HW_DCP_CH0STAT)
DCP Channel 0 Options Register (HW_DCP_CH0OPTS)
DCP Channel 1 Command Pointer Address Register
(HW_DCP_CH1CMDPTR)
DCP Channel 1 Semaphore Register (HW_DCP_CH1SEMA)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Register name
HW_DCP memory map
(in bits)
Width
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Freescale Semiconductor, Inc.
Reset value
F080_0000h
1000_0000h
0000_0000h
0000_0404h
0007_0001h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
13.3.10/1034
13.3.11/1036
13.3.12/1038
13.3.13/1038
13.3.14/1039
13.3.15/1039
13.3.16/1040
13.3.17/1040
13.3.18/1041
13.3.19/1043
13.3.20/1044
13.3.21/1045
13.3.1/1025
13.3.2/1027
13.3.3/1028
13.3.4/1030
13.3.5/1031
13.3.6/1031
13.3.7/1032
13.3.8/1033
13.3.9/1034
Section/
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