MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1429

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Freescale Semiconductor, Inc.
8002_C1A0
8002_C1B0
8002_C1C0
8002_C1D0
8002_C1E0
8002_C110
8002_C120
8002_C130
8002_C140
8002_C150
8002_C160
8002_C170
8002_C180
8002_C190
8002_C1F0
8002_C200
8002_C210
8002_C220
8002_C230
8002_C240
8002_C250
Absolute
address
(hex)
Customer Capability Shadow Register
(HW_OCOTP_CUSTCAP)
LOCK Shadow Register OTP Bank 2 Word 0
(HW_OCOTP_LOCK)
Value of OTP Bank2 Word1 (Freescale OPS0)
(HW_OCOTP_OPS0)
Value of OTP Bank2 Word2 (Freescale OPS1)
(HW_OCOTP_OPS1)
Value of OTP Bank2 Word3 (Freescale OPS2)
(HW_OCOTP_OPS2)
Value of OTP Bank2 Word4 (Freescale OPS3)
(HW_OCOTP_OPS3)
Value of OTP Bank2 Word5 (Unassigned0)
(HW_OCOTP_UN0)
Value of OTP Bank2 Word6 (Unassigned1)
(HW_OCOTP_UN1)
Value of OTP Bank2 Word7 (Unassigned2)
(HW_OCOTP_UN2)
Shadow Register for OTP Bank3 Word0 (ROM Use 0)
(HW_OCOTP_ROM0)
Shadow Register for OTP Bank3 Word1 (ROM Use 1)
(HW_OCOTP_ROM1)
Shadow Register for OTP Bank3 Word2 (ROM Use 2)
(HW_OCOTP_ROM2)
Shadow Register for OTP Bank3 Word3 (ROM Use 3)
(HW_OCOTP_ROM3)
Shadow Register for OTP Bank3 Word4 (ROM Use 4)
(HW_OCOTP_ROM4)
Shadow Register for OTP Bank3 Word5 (ROM Use 5)
(HW_OCOTP_ROM5)
Shadow Register for OTP Bank3 Word6 (ROM Use 6)
(HW_OCOTP_ROM6)
Shadow Register for OTP Bank3 Word7 (ROM Use 7)
(HW_OCOTP_ROM7)
Shadow Register for OTP Bank4 Word0 (Data Use 0)
(HW_OCOTP_SRK0)
Shadow Register for OTP Bank4 Word1 (Data Use 1)
(HW_OCOTP_SRK1)
Shadow Register for OTP Bank4 Word2 (Data Use 2)
(HW_OCOTP_SRK2)
Shadow Register for OTP Bank4 Word3 (Data Use 3)
(HW_OCOTP_SRK3)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_OCOTP memory map (continued)
Register name
(in bits)
Chapter 20 On-Chip OTP (OCOTP) Controller
Width
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
Reset value
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
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page
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