MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1730
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Operation
Figure 27-1
27.2 Operation
The I
1730
• Master transactions are composed of one or more DMA commands chained together.
• When the slave interface is enabled, it immediately goes into address search mode and
• The I
The first byte conveys the slave address and read/write bit for the first command. If the
entire transaction is an I
command. If the command is an I
are required to handle it.
searches for a start event. It then looks for a match on its programmable device address.
As soon as the address byte is matched, it is acknowledged on the I
SCL clock is held low until released by software. The address phase initiates a CPU
interrupt, if a slave address match is detected. Software then reads the address LSB to
determine whether to use a read or write DMA command to complete the slave
transaction.
2
C Interface on the i.MX28 includes the following external pins:
2
C block does not support CBUS (start byte is 00000001) device in master mode.
shows a block diagram of the I
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
I 2 C_ SDA
I 2 C_ SCL
ARM Core
APB Bridge
Figure 27-1. I
APBX Master
2
C write command, then it can be sent by a single DMA
Shared APBX DMA
AHB
2
2
C read transaction, then at least two DMA commands
C Interface Block Diagram
SRAM
DMA Interface
APBX Bridge / DMA
I 2C Programmable Registers
2
FSM
Input Sync and I
C interface implemented on the i.MX28.
and FIFOs
Generation
Slave Search
2C_CLK
Engine
24 - MHz
Divide
XTAL
I 2C
Osc.
by n
Freescale Semiconductor, Inc.
2
C bus and then the
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