MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1610
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
- Current page: 1610 of 2327
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10 100Mbps Ethernet ENET-MAC Core Features
26.3.2.3 IEEE 1588 Functions
1610
• IPv4 and IPv6 support
• Transparent passing of frames of other types and protocols
• Support for VLAN tagged frames according to IEEE 802.1q with transparent forwarding
• Automatic IP-header and payload (protocol specific) checksum calculation and
• Automatic IP-header and payload (protocol specific) checksum generation and automatic
• Support for IP and TCP, UDP, ICMP data for checksum generation and checking
• Full header options support for IPv4 and TCP protocol headers
• IPv6 support limited to datagrams with base header only. Datagrams with extension
• Statistics information for received IP and protocol errors
• Configurable automatic discard of erroneous frames
• Configurable automatic Host-to-Network (RX) and Network-to-Host (TX) byte order
• Configurable padding remove for short IP datagrams on receive
• Configurable Ethernet Payload alignment to allow for 32-bit word aligned header and
• Programmable Store & Forward operation with clock and rate decoupling FIFOs
• Support for all IEEE 1588 Frames
• Reference Clock can be chosen independently of the Network speed
• Software Programmable Precise Time-Stamping of Ingress Frames and Egress Frames
• Timer monitoring capabilities for System calibration and timing accuracy management
• Precise time stamping of external events with programmable interrupt generation
• Programmable event and interrupt generation for external system control
• Hardware and Software controllable timer synchronization
of VLAN tag and control field
verification on receive
insertion on transmit configurable on a per-frame basis
headers are passed transparently unmodifed/unchecked
conversion for IP and TCP/UDP/ICMP headers within the frame
payload processing
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.
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