MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1242

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

GPMI NAND Mode
GPMI can support data bus speeds of up to 50 MHz x 8 bits. The actual read/write strobe
timing parameters are adjusted as indicated in the GPMI register descriptions. See
Structure
15.2.3 Basic NAND Timing
The following figure illustrates the operation of the timing parameters in NAND mode.
15.2.4 High-Speed NAND Timing
In high-speed NANDs, the read data may not be valid until after the read strobe (RDN)
deasserts. This is the case when the minimum tDS is programmed to achieve higher
bandwidth. The GPMI implements a feedback read strobe to sample the read data. The
feedback read strobe can be delayed to support fast NAND EDO (Extended Data Out)
timing where the read strobe may deassert before the read data is valid, and read data is
valid for some time after read strobe. NAND EDO timings is applied typically for read
cycle frequency above 33 MHz.See
The GPMI provides control over the amount of delay applied to the feedback read strobe.
This delay depends on the maximum read access time (tREA) of the NAND and the read
pulse width (tRP) used to access the NAND. tRP is specified by
HW_GPMI_TIMING0_DATA_SETUP register. When (tREA + 4 ns) is less than tRP, no
delay is required to sample the NAND read data. (The 4 ns provides adequate data setup
time for the GPMI.) In this case, set HW_GPMI_CTRL1_HALF_PERIOD=0;
HW_GPMI_CTRL1_RDN_DELAY=0; HW_GPMI_CTRL1_DLL_ENABLE=0.
When (tREA + 4 ns) is greater than or equal to tRP, a delay of the feedback read strobe is
required to sample the NAND read data. This delay is equal to the difference between these
two timings:
DELAY= tREA+4 ns - tRP.
Since the GPMI delay chain is limited to 16 ns maximum, if DELAY > 16 ns then increase
tRP by increasing the value of HW_GPMI_TIMING0_DATA_SETUP until DELAY is
less than or equal to 16 ns.
1242
for more information about setting GPMICLK.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
GPMI_CE[7:0] /
GPMI_DATA
GPMI_OEn/
GPMI_WRn
ALE / CLE
Figure 15-2. BASIC NAND Timing
Figure
TAS
15-3.
TDS
Data0
TDH
Data1
TDH
Freescale Semiconductor, Inc.
Clock