MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1662

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
1662
TS_TIMER
TS_AVAIL
WAKEUP
RSRVD1
EBERR
Field
GRA
14 0
RXF
RXB
TXF
TXB
PLR
UN
MII
LC
RL
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Graceful stop complete.This interrupt is asserted after the transmitter is put into a pause state after completion
of the frame currently being transmitted. See
stop.
Note: The GRA interrupt is asserted only when the TX transitions into the stopped state. If this bit is cleared
(by writing 1) and the TX is still stopped, the bit will not become set again.
Transmit frame interrupt. This bit indicates a frame has been transmitted and the last corresponding buffer
descriptor has been updated (Signal dma_txf_int asserted).
Transmit buffer interrupt. This bit indicates a transmit buffer descriptor has been updated (Signal dma_txb_int
asserted).
Receive frame interrupt. This bit indicates a frame has been received and the last corresponding buffer
descriptor has been updated (Signal dma_rxf_int asserted).
Receive buffer interrupt. This bit indicates a receive buffer descriptor not the last in the frame has been
updated (Signal dma_rxb_int asserted).
MII interrupt. This bit indicates the MII has completed the data transfer requested.
Ethernet bus error. This bit indicates a system bus error occurs when a DMA transaction is underway (Signal
dma_eberr_int asserted). When the EBERR bit is set, ETHER_EN is cleared, halting frame processing by
the MAC. When this occurs, software needs to insure proper actions (possibly resetting the system) to
resume normal operation.
Late collision. This bit indicates a collision occurs beyond the collision window (slot time) in half duplex mode.
The frame truncates with a bad CRC and the remainder of the frame is discarded.
Collision retry limit. This bit indicates a collision occurs on each of 16 successive attempts to transmit the
frame. The frame is discarded without being transmitted and transmission of the next frame commences.
This error can only occur in half duplex mode.
Transmit FIFO underrun. This bit indicates the transmit FIFO became empty before the complete frame was
transmitted. A bad CRC is appended to the frame fragment and the remainder of the frame is discarded.
Payload receive error. This bit indicates a frame was received with a payload length error.
Node Wake Up Request Indication. Read only status bit to indicate that a Magic Packet has been detected.
Will act only if ECR(MAGIC_ENA) is 1.
Transmit Timestamp Available. Indicates that the timestamp of the last transmitted Timing Frame is available
in the register TS_TIMESTAMP.
The adjustable timer reached the period or offset events.
Reserved bits. Write as 0.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_ENET_MAC_EIR field descriptions (continued)
Graceful Transmit Stop (GTS)
Description
for conditions that lead to graceful
Freescale Semiconductor, Inc.