MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1823

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

For each Frame processed by the switch engine, two 32-Bit records (Record A(0) and Record
B(1)) are written in the Information FIFO, Record A is written first.
The MAC address available in Records A(0) and B(1) is the source MAC address of the
Frame. Record A holds the first 4 bytes of the frame source address (1st=A[7:0],
4th=A[31:24]), Record B the last 2 bytes (5th=B[7:0], 6th=B[15:8]).
The Hash code in Record B is calculated, with the Source MAC Address, with the same
Hash Polynomial used for Look-Up (as defined in 5.8.2 page 36) and the 4-Bit port number
defines the Port / MAC Address association.
When information for at least one Frame (Two Records) is available, the status indication
in register LRN_STATUS is set to '1'. To read the Frame records, the register LRN_REC_0
(Record A) must be read first followed by a read to LRN_REC_1 (Record B).
The learning task (software) is using this information and then executes as follows:
Freescale Semiconductor, Inc.
1. For every frame received, the source address with port and timestamp information is
stored in the address lookup table. The following information are stored for each entry:
• MAC address: the 48-bit address is stored in the table.
A read to LRN_REC_1 triggers the retrieval of the next record
pair from the FIFO if any.
Figure 29-11. Frame Information Records - 8-Bit Hash Values
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Frame Record A
Frame Record B
Figure 29-10. Learning Interface Overview
31
4 Reserved Bits
Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH)
4-Bit Port Number
Read
Learning Interface
De-Queuing Control
Note
MAC Address (48 Bits)
Status
8-Bit hash code
0
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