MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2084

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
2084
WORD_LENGTH
YCBCR422_CSC
LCDIF_MASTER
DATA_FORMAT_
DATA_FORMAT_
LCD_DATABUS_
CSC_DATA_
RGB_TO_
SWIZZLE
Reserved
RSRVD0
WIDTH
16_BIT
18_BIT
13 12
11 10
Field
9 8
7
6
5
4
3
2
0x0
0x1
0x1
0x2
0x3
This field specifies how to swap the bytes after the data has been converted into an internal representation
of 24 bits per pixel and before it is transmitted over the LCD interface bus. The data is always transmitted
with the least significant byte/hword (half word) first after the swizzle takes place. So, INPUT_DATA_SWIZZLE
takes place first on the incoming data, and then CSC_DATA_SWIZZLE is applied. The swizzle function is
independent of the WORD_LENGTH or the LCD_DATABUS_WIDTH fields. If RGB_TO_YCRCB422_CSC
bit is set, the swizzle occurs on the Y, Cb, Cr values. The supported swizzle configurations are:
0x0
0x0
0x1
0x1
0x2
0x3
LCD Data bus transfer width.
0x0
0x1
0x2
0x3
Input data format.
0x0
0x1
0x2
0x3
Set this bit to 1 to enable conversion from RGB to YCbCr colorspace. See the HW_LCDIF_CSC_ registers
for further details.
This bit is reserved.
Reserved, always set to zero.
Set this bit to make the LCDIF act as a bus master. If this bit is reset, the LCDIF will act in its traditional DMA
slave mode.
Reserved bits. Write as 0.
When this bit is 1 and WORD_LENGTH = 0, it implies that the the 16-bit data is in ARGB555 format. When
this bit is 0 and WORD_LENGTH = 0, it implies that the 16-bit data is in RGB565 format. When
WORD_LENGTH is not 0, this bit is a dont care.
Used only when WORD_LENGTH = 2, i.e. 18-bit.
LITTLE_ENDIAN — Little Endian byte ordering (same as NO_SWAP).
BIG_ENDIAN_SWAP — Big Endian swap (swap bytes 0,3 and 1,2).
SWAP_ALL_BYTES — Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
HWD_SWAP — Swap half-words.
HWD_BYTE_SWAP — Swap bytes within each half-word.
NO_SWAP — No byte swapping.(Little endian)
LITTLE_ENDIAN — Little Endian byte ordering (same as NO_SWAP).
BIG_ENDIAN_SWAP — Big Endian swap (swap bytes 0,3 and 1,2).
SWAP_ALL_BYTES — Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
HWD_SWAP — Swap half-words.
HWD_BYTE_SWAP — Swap bytes within each half-word.
16_BIT — 16-bit data bus mode.
8_BIT — 8-bit data bus mode.
18_BIT — 18-bit data bus mode.
24_BIT — 24-bit data bus mode.
16_BIT — Input data is 16 bits per pixel.
8_BIT — Input data is 8 bits wide.
18_BIT — Input data is 18 bits per pixel.
24_BIT — Input data is 24 bits per pixel.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_LCDIF_CTRL field descriptions (continued)
Description
Freescale Semiconductor, Inc.