MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1260

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

BCH Overview
The BCH decoder processes code words in a 4-step fashion:
The BCH block, shown in the figure, was designed to operate in a pipelined fashion to
maximize throughput. Aside from the initial latency to fill the pipeline stages, the BCH
throughput is faster than the fastest GPMI read rate of 2 cycles/byte. Thus, the bottleneck
in performing NAND reads and error corrections is the GPMI read rate. Current GPMI read
rates are approximately 3 cycles/byte for the current generation of NAND flash. The CPU
is not directly involved in generating parity symbols, checking for errors, or correcting
them.
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1. Syndrome Calculation (SC): This is the process of reading in all of the symbols of the
2. Key Equation Solver (KES): The syndromes represent 2t-linear equations with
3. Chien Search (CS): This block takes input from the KES block and uses the Chien
4. Correction: this block has to convert the symbol index and mask information to memory
codeword and continuously dividing by the generator polynomial for the field. 2*t
syndromes must be calculated for each codeword and inspection of the syndromes
determines if there are errors: a non-zero set of syndromes indicates one or more errors.
This process is implemented parallel hardware to minimize processing time since it
must be done every time the decode is performed.
2t-unknown variables. The process of solving these equations and selecting from the
numerous solutions constitutes the KES module. When the KES block completes its
operations, it generates an error locator polynomial (sigma) that is used in the proceeding
block to determine the locations and values of the errors.
Algorithm for finding the locations of the errors based on the error locator polynomial.
The method basically involves substituting all 8191 symbols from the GF(8192) into
the locator polynomial. All evaluations that produce a zero solution indicate locations
of the various errors. Since each located error corresponds to a single bit, the bit in the
original data may be corrected by simply flipping the polarity of the incorrect location.
byte indexes and masks.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.