MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 694

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
9.4.2 PINCTRL Pin Mux Select Register 0 (HW_PINCTRL_MUXSEL0)
The PINCTRL Pin Mux Select Register provides pin function selection for 8 pins in bank0.
HW_PINCTRL_MUXSEL0: 0x100
HW_PINCTRL_MUXSEL0_SET: 0x104
HW_PINCTRL_MUXSEL0_CLR: 0x108
HW_PINCTRL_MUXSEL0_TOG: 0x10C
This register allows the programmer to select which hardware interface blocks drive the 8
pins shown above.
Address:
694
Reset
PRESENT1
PRESENT0
IRQOUT4
IRQOUT3
IRQOUT2
IRQOUT1
IRQOUT0
Bit
W
RSRVD1
R
Field
19 5
21
20
4
3
2
1
0
31
0
HW_PINCTRL_MUXSEL0 8001_8000h base + 100h offset = 8001_8100h
30
0
GPIO Functionality Present. 0: GPIO functionality for Pin Control Bank 1 is not present in this product. 1:
GPIO functionality for Bank 1 is present.
GPIO Functionality Present. 0: GPIO functionality for Pin Control Bank 0 is not present in this product. 1:
GPIO functionality for Bank 0 is present.
Always write zeroes to this field.
Read-only view of the interrupt collector GPIO4 signal, sourced from the combined IRQ outputs from bank
4.
Read-only view of the interrupt collector GPIO3 signal, sourced from the combined IRQ outputs from bank
3.
Read-only view of the interrupt collector GPIO2 signal, sourced from the combined IRQ outputs from bank
2.
Read-only view of the interrupt collector GPIO1 signal, sourced from the combined IRQ outputs from bank
1.
Read-only view of the interrupt collector GPIO0 signal, sourced from the combined IRQ outputs from bank
0.
29
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_PINCTRL_CTRL field descriptions (continued)
28
0
27
0
26
0
25
0
24
RSRVD0
0
Description
23
0
22
0
21
0
20
0
Freescale Semiconductor, Inc.
19
0
18
0
17
0
16
0