MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1400

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
19.4.41 AHB Layer 1 Transfer Count Register
The AHB Layer 1 Transfer Count Register counts the number of AHB bus cycles during
which a transfer is active on AHB Layer 0.
This field counts the number of AHB cycles in which a master was requesting a transfer,
and the slave had not responded. This includes cycles in which it was requesting transfers
but was not granted them, as well as cycles in which it was granted and driving the bus but
the targeted slave was not ready. The master selects in
HW_DIGCTL_CTRL_MASTER_SELECT are used in the arbiter to mask which master\'s
cycles are actually recorded here.
EXAMPLE
NumberCycles = HW_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT_RD();
Address:
Re-
1400
set
Bit
W
R
L2_MASTER_
L1_MASTER_
31
SELECT
SELECT
0
COUNT
Field
15 8
Field
31 0
7 0
30
0
29
0
HW_DIGCTL_L1_AHB_ACTIVE_CYCLES
8001_C370h
(HW_DIGCTL_L1_AHB_ACTIVE_CYCLES)
28
HW_DIGCTL_AHB_STATS_SELECT field descriptions (continued)
0
0x4
0x8
0x10
0x20
Set various bits of this bit field to one to enable performance monitoring in the AHB Layer 2 arbiter for the
corresponding AHB master. Bits [7:1] are currently reserved and should not be set
0x1
Set various bits of this bit field to one to enable performance monitoring in the AHB Layer 1 arbiter for the
corresponding AHB master. Bits [7:1] are currently reserved and should not be set
0x1
This field contains the count of AHB bus cycles during which a master was active on the AHB Layer 1.
27
0
HW_DIGCTL_L1_AHB_ACTIVE_CYCLES field descriptions
26
0
ARMD — Select ARM DATA Master.
ARMI — Select ARM Instruction Master.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
USB0 — Select USB0 Master.
USB1 — Select USB1 Master.
UDMA0 — Select UDMA0 Master.
UDMA1 — Select UDMA1 Master.
25
0
24
0
23
0
22
0
21
0
20
0
19
0
18
0
17
0
8001_C000h base + 370h offset =
COUNT
16
0
15
0
Description
Description
14
0
13
0
12
0
11
0
10
0
0
9
0
8
Freescale Semiconductor, Inc.
0
7
0
6
0
5
0
4
3
0
0
2
0
1
0
0