MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1122

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
14.8.18 DRAM Control Register 17 (HW_DRAM_CTL17)
This is a DRAM configuration register.
1122
POWER_DOWN
OBSOLETE
MODEREG
WRITE_
RSVD3
RSVD2
RSVD1
START
31 25
23 17
Field
15 8
7 1
24
16
0
Always write zeroes to this field.
Write mode register data to the DRAMs. WRITE-ONLY
Writes mode register information into the memory devices. The user should program the appropriate
mrY_data_X parameters with valid information based on the memory type being used. All of the mode
registers that are relevant for the memory type specified in the dram_class parameter will be written on each
write_modereg setting. This parameter will always read back as 'b0.
The mode registers are automatically written at initialization of the EMI. There is no need to initiate a mode
register write after setting the start parameter in the EMI unless some value in these registers needs to be
changed after initialization.
This parameter may not be changed when the memory is in power-down mode (when the CKE input is
de-asserted).
Always write zeroes to this field.
Disable clock enable and set DRAMs in power-down state.
When this parameter is set to 'b1, the EMI will complete processing of the current burst for the current
transaction (if any), issue a pre-charge all command and then disable the clock enable signal to the DRAM
devices. Any subsequent commands in the command queue will be suspended until this parameter is cleared
to 'b0.
'b0 = Enable full power state.
'b1 = Disable the clock enable and power down the EMI.
Always write zeroes to this field.
Always write zeroes to this field.
Initiate cmd processing in the controller.
Prior to setting this parameter to 1'b1, the EMI will not issue any commands to the DRAM devices or respond
to any signal activity except for reading and writing parameters and accepting traffic that the customer may
send to the EMI internal queues. Once this parameter is set to 1'b1, the EMI will respond to inputs from the
ASIC and begin to process memory access commands. Note that resetting this parameter to 1'b0 will not
shut off traffic. However, cycling this parameter to 1'b0 and then resetting it to 1'b1 will reset the digital DLL
to a new input clock frequency if desired. This protocol is described in detail in section
Frequency. Note: Until the initialization complete bit is set in the int_status parameter and the dfi_init_complete
signal is asserted from the PHY, commands will not be accepted into the core command queue.
'b0 = Controller is not in active mode.
'b1 = Initiate active mode for the EMI.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_DRAM_CTL16 field descriptions
Description
Freescale Semiconductor, Inc.
Changing Input Clock