MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1562

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Functional Description
will remain FULL, as explained in
by writing to the C/S word to force an EMPTY code after reading the MB, the MB is actually
deactivated from any currently ongoing matching process. As a result, a newly received
frame matching the ID of that MB may be lost. In summary: never do polling by reading
directly the C/S word of the MBs. Instead, read the IFLAG registers.
Note that the received ID field is always stored in the matching MB, therefore the contents
of the ID field in an MB may change if the match was due to masking. Note also that
FlexCAN does receive frames transmitted by itself if there exists an Rx matching MB,
provided the SRX_DIS bit in the MCR is not asserted. If SRX_DIS is asserted, FlexCAN
will not store frames transmitted by itself in any MB, even if it contains a matching MB,
and no interrupt flag or interrupt signal will be generated due to the frame reception.
To be able to receive CAN frames through the FIFO, the ARM must enable and configure
the FIFO during Freeze Mode (see
from FIFO, the ARM should service the received frame using the following procedure:
25.4.5 Matching Process
The matching process is an algorithm executed by the MBM that scans the MB memory
looking for Rx MBs programmed with the same ID as the one received from the CAN bus.
If the FIFO is enabled, the 8-entry ID table from FIFO is scanned first and then, if a match
is not found within the FIFO table, the other MBs are scanned. In the event that the FIFO
is full, the matching algorithm will always look for a matching MB outside the FIFO region.
When the frame is received, it is temporarily stored in a hidden auxiliary MB called Serial
Message Buffer (SMB). The matching process takes place during the CRC field of the
received frame. If a matching ID is found in the FIFO table or in one of the regular MBs,
the contents of the SMB will be transferred to the FIFO or to the matched MB during the
sixth bit of the End-Of-Frame field of the CAN protocol. This operation is called move-in.
If any protocol error (CRC, ACK, and so on) is detected, than the move-in operation does
not happen.
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• Read the Control and Status word (optional – needed only if a mask was used for IDE
• Read the ID field (optional – needed only if a mask was used)
• Read the Data field
• Clear the frames available interrupt (mandatory – release the buffer and allow the ARM
and RTR bits)
to read the next FIFO entry)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Table
Rx
FIFO). Upon receiving the frames available interrupt
25-2. If the ARM tries to workaround this behavior
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