MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1069
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Freescale Semiconductor, Inc.
• Priority Definition
• Register Port
• Port Bridging
• Buffering
Command priority is defined based on the port and the command type. For each port
Y, there is an axiY_r_priority parameter which defines priorities for all read commands
and an axiY_w_priority parameter which defines priorities for all write commands.
Supported priority values range from 0 to 7, with 0 as the highest priority.
The 32-bit AHB register port is fixed in Asynchronous mode between the AHB bus
clock domain and the emi_clk domain.
The following table shows the front-end bridge settings.
Each AXI interface contains a command, a read and a write FIFO, and a response
storage array. In addition, each programmable port contains an asynchronous response
FIFO to synchronize the memory response to the port clock domain when operating
asynchronously.
Port Number
Port Num-
ber
Port 0
Port 1
Port 2
Port 3
Port
Port
Port
0
1
2
Port Data
Bus Connection
Width
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
AXI
AHB
AHB
AHB
64
32
32
Clock Domain Type
Table 14-3. Front-End Bridge Settings
Internal Port Type
Programmable
Programmable
Programmable
Native AXI
AHB-AXI
Bridged
AHB-AXI
Bridged
AHB-AXI
Bridged
Table 14-4. AXI Port FIFOs
FIFO Depth
Command
4
2
2
Write FIFO
Depth
Chapter 14 External Memory Interface (EMI)
8
8
8
Read FIFO
Depth
8
8
8
FIFO Depth
Response
4
4
4
Storage Ar-
Response
ray Depth
1069
8
4
4
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