MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1163

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Address:
Re-
14.8.63 DRAM Control Register 68 (HW_DRAM_CTL68)
This is a DRAM configuration register.
Freescale Semiconductor, Inc.
set
Bit
W
R
CLK_DISABLE
CLK_ENABLE
TDFI_DRAM_
TDFI_DRAM_
DRAM_CLK_
TDFI_CTRL_
31
0
ENABLE
RSVD4
RSVD3
RSVD2
RSVD1
DELAY
31 28
27 24
23 19
18 16
15 12
Field
11 8
7 4
3 0
RSVD4
30
0
29
0
HW_DRAM_CTL67
28
0
Always write zeroes to this field.
Delay from DFI clock enable to memory clock enable.
Holds the DFI tdram_clk_enable timing parameter. This parameter is currently unused in the EMI.
Always write zeroes to this field.
Delay from DFI clock disable to memory clock disable.
Holds the DFI tdram_clk_disable timing parameter. This parameter should be programmed with the number
of cycles that the PHY requires to disable the clock after the dfi_dram_clk_disable signal is asserted.
Always write zeroes to this field.
Set value for the dfi_dram_clk_disable signal.
Sets value for the DFI output signal dfi_dram_clk_disable. Bit [0] controls CS0, Bit [1] controls CS1. For
each bit:
'b0 = Memory clock/s should be disabled.
'b1 = Memory clock/s should be active.
Always write zeroes to this field.
Delay from DFI command to memory command.
Holds the DFI tctrl_delay timing parameter.This parameter should be programmed with the number of cycles
that the PHY requires to send a power-down or self-refresh command to the DRAM devices.
27
CLK_ENABLE
0
TDFI_DRAM_
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
23
0
HW_DRAM_CTL67 field descriptions
800E_0000h base + 10Ch offset = 800E_010Ch
22
0
RSVD3
21
0
20
0
19
0
DRAM_CLK_
18
0
DISABLE
TDFI_
17
0
16
0
15
0
Description
RSVD2
14
0
13
0
12
0
Chapter 14 External Memory Interface (EMI)
11
0
DRAM_CLK_
ENABLE
10
0
0
9
0
8
0
7
RSVD1
0
6
0
5
0
4
3
0
TDFI_CTRL_
DELAY
0
2
0
1
1163
0
0