MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 843

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Chapter 10
Clock Generation and Control (CLKCTRL)
10.1 Clock Generation and Control (CLKCTRL) Overview
The clock control module, or CLKCTRL, generates the clock domains for all components
in the i.MX28 system. The crystal clock or PLL clock are the two fundamental sources used
to produce all the clock domains. For lower performance and reduced power consumption,
the crystal clock is selected. The PLL is selected for higher performance requirements but
requires increased power consumption. In most cases, when the PLL is used as the source,
a phase fractional divider (PFD) can be programmed to reduce the PLL clock frequency by
up to a factor of 2.
The PLL and PFD clocks are used as reference clock sources to drive digital clock dividers
in the clock control module. These reference clocks, or ref_<clock>, drive the digital clock
dividers in CLKCTRL. The digital clock dividers have three modes of operation, integer
divide mode, fractional divide mode, and gated clock mode. The details of these three modes
will be described to understand which mode should be selected to achieve the desired
frequency.
All programming control for system clocks are contained in the CLKCTRL module. All
clock domains have a programmable clock frequency to meet application requirements.
Also, all analog clock control programming is done indirectly through the CLKCTRL
module. This contains the complexity of overall system clock selection to a single device.
Also, the hardware used to generate all clock domains is replicated. Following is a description
of all clock domains in the i.MX28 system.
10.2 Clock Structure
The reference clocks are used in CLKCTRL as fundamental clock sources to produce clock
domains throughout the system. A reference clock can be either the crystal clock, 480 MHz
PLL, or PFD output from the analog module. The selected reference clock is used by a
digital clock divider to produce the desired clock domain. The table below summarizes all
available reference clocks used within the CLKCTRL and all clock domains used in the
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.
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