MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1819

no-image

MCIMX281AVM4B

Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets

Specifications of MCIMX281AVM4B

Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
29.4.6.5 Bridge Control Protocol Identification
To allow for implementation of bridge control protocols like the Spanning tree protocol,
all control frames (Bridge Protocol Data Units, BPDU) are marked when they enter the
switch. The mark then can be used by the Input Port Blocking function to drop the frame
after the address learning (see also 5.10.5 page 43).
In addition, the function can be configured to pass all frames or to pass only control frames
(that is, covering spanning tree port states such as blocking, listening, learning) and discard
all other frames.
29.4.7 Input Port Selection
The port selection constantly checks (polling) all input ports for available data and if any
data is available, a port is selected and frame data is read from the input. After one frame
has been read, another port is selected, even if further data is available on the current port.
This means for the application on a port atlantic input interface, that it is not allowed to
perform back-to-back frame transfers to the switch. Instead the application must wait for a
new selection after one frame has been transferred.
29.4.8.1 Overview
A hash code is calculated using the frame destination MAC address. It is used as an entry
(address) to a table, which contains, for each hash value MAC addresses with destination
port number and validity information.
As one hash code value can represent more than one MAC address, the memory implements
for each pointer, up to eight MAC address entries, which are searched linearly.
Freescale Semiconductor, Inc.
• else if VLAN classification is enabled and VLAN tag found => map priority according
• else if MAC classification is enabled and MAC address found => take priority from
• else use default priority as specified in PRIORITY_CFG.
VLAN_PRIORITY table
address table, if it is a static entry
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH)
1819

Related parts for MCIMX281AVM4B