MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1001
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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13.1.1 DCP Limitations for Software
While the DCP module has been designed to be as flexible as possible, there are a few
limitations to which software must adhere:
Freescale Semiconductor, Inc.
• Buffer sizes for all operations MUST be aligned to the natural size of the transfer
• The DCP module supports buffer operations to any byte alignment, but performance
• Hash operations are limited to a 512 Mbyte buffer size. The hardware only implements
• For chained hashing operations (operations involving multiple descriptors), every
• Key values cannot be written while the AES block is active. This limitation exists
• The byte-swap controls can only be used with modulo-4 length buffers. For
• The word-swap controls are only useful with cipher operations, because the logic forms
• DCP only supports writes to word boundaries to OCRAM. This is not required for EMI
algorithm used. Memcopy operations can transfer any number of bytes (one-byte
granularity) and AES operations must be multiples of 16 bytes (four-word granularity).
For all operations, if the byte count is not a word granularity, the hardware rounds up
to the next word. Hashing is supported at a byte granularity.
will be improved if buffers are aligned to a four-byte boundary, since fetch/store
operations can be performed without having to do byte operations to accommodate the
misaligned addresses.
a 32-bit hash length counter instead of the 64-bit counter supported by the
SHA-1/SHA-256 algorithm (counter counts bits, not bytes, therefore a total of 512
Mbytes).
descriptor except the last must have a byte count that is a 16-word multiple (granularity
of the hash algorithm).
because the key RAM is in use while AES is operational. Any writes from the APB
cannot be held in wait states; therefore, the RAM must be accessible during key writes.
non-modulo-4 lengths, the final partial word will contain incorrect data. Any address
alignment can be used with byte swapping, however.
the 128-bit cipher data from four words from system memory. The word-swap controls
are ignored for memcopy or hashing operations.
DRAM address.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 13 Data Co-Processor (DCP)
1001
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