MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1321

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Chapter 17 Synchronous Serial Ports (SSP)
SSP_SCK
SSn
MSB
LSB
MOSI/MISO
4 to 16 bits
Figure 17-9. Texas Instruments Synchronous Serial Frame Format (Single Transfer)
In this mode, SSP_SCK and SSn are forced low, and the transmit data line MOSI is
three-stated whenever the SSP is idle. Once the bottom entry of the FIFO contains data,
SSn is pulsed high for one SSP_SCK period. The value to be transmitted is also transferred
from the FIFO to the serial shift register of the transmit logic. On the next rising edge of
SSP_SCK, the MSB of the 4-to-16-bit data frame is shifted out on the SSPRXD pin by the
off-chip serial slave device.
Both the SSP and the off-chip serial slave device then clock each data bit into their serial
shifter on the falling edge of each SSP_SCK. The received data is transferred from the serial
shifter to the FIFO on the first rising edge of SSP_SCK after the LSB has been latched.
Figure 17-10
shows the Texas Instrument synchronous serial frame format when back-to-back
frames are transmitted.
SSP_SCK
SSn
MSB
LSB
MOSI/MISO
4 to 16 bits
Figure 17-10. Texas Instruments Synchronous Serial Frame Format (Continuous Transfer)
17.8 SD/SDIO/MMC Mode
This mode is used to provide high performance with SD, SDIO, MMC, and high-speed
(4-bit and 8-bit) MMC cards. When running 4-bit and 8-bit modes, the SSP has the capability
of SDR and DDR operations. Power-on and alternate boot operations are also supported.
SD/MMC mode supports simultaneous command and data transfers. Commands are sent
to the card and responses are returned to the host on the CMD line. Register data, such as
card information, is sent as a command response and is therefore on the CMD line. Block
data read from or written to the card's flash is transferred on the DAT line(s). The SSP also
supports the SDIO IRQ.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.
1321