MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2324

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Examples
BF_WRn(TIMROT_TIMCTRLn, i, PRESCALE, BV_TIMROT_TIMCTRLn_PRESCALE_DIV_BY_1);
// Write multiple fields
// Read a field
iRun = BF_RDn(TIMROT_TIMCTRLn, i, IRQ);
}
39.5.10 Correct Way to Soft Reset a Block
// Prepare for soft-reset by making sure that SFTRST is not currently
// asserted. Also clear CLKGATE so we can wait for its assertion below.
HW_GPMI_CTRL0_CLR(BM_GPMI_CTRL0_SFTRST);
// Wait at least a microsecond for SFTRST to deassert. In actuality, we
// need to wait 3 GPMI clocks, but this is much easier to implement.
musecs = hw_profile_GetMicroseconds();
while (HW_GPMI_CTRL0.B.SFTRST || (hw_profile_GetMicroseconds() - musecs <
DDI_NAND_HAL_GPMI_SOFT_RESET_LATENCY));
// Also clear CLKGATE so we can wait for its assertion below.
HW_GPMI_CTRL0_CLR(BM_GPMI_CTRL0_CLKGATE);
// Now soft-reset the hardware.
HW_GPMI_CTRL0_SET(BM_GPMI_CTRL0_SFTRST);
// Poll until clock is in the gated state before subsequently
// clearing soft reset and clock gate.
while (!HW_GPMI_CTRL0.B.CLKGATE)
{
; // busy wait
}
// bring GPMI_CTRL0 out of reset
HW_GPMI_CTRL0_CLR(BM_GPMI_CTRL0_SFTRST);
// Wait at least a microsecond for SFTRST to deassert. In actuality, we
// need to wait 3 GPMI clocks, but this is much easier to implement.
musecs = hw_profile_GetMicroseconds();
while (HW_GPMI_CTRL0.B.SFTRST || (hw_profile_GetMicroseconds() - musecs <
DDI_NAND_HAL_GPMI_SOFT_RESET_LATENCY));
HW_GPMI_CTRL0_CLR(BM_GPMI_CTRL0_CLKGATE);
// Poll until clock is in the NON-gated state before returning.
while (HW_GPMI_CTRL0.B.CLKGATE)
{
; // busy wait
}
39.5.10.1 Pinmux Selection During Reset
For proper I
block out of reset. Failure to select the I
of reset will cause the I
reset.
39.5.10.1.1 Correct and Incorrect Reset Examples
Incorrect:
2324
BF_CS2n(TIMROT_TIMCTRLn, i, RELOAD, 1, SELECT, BV_TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL);
Clear I
... Setup ...
I
2
C PinMux Selections
2
2
C SFTRST/CLKGATE
C operation, the appropriate pinmux(s) must be selected before taking the
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
2
C clock to operate incorrectly and will require another I
2
C pinmux selections before taking the block out
Freescale Semiconductor, Inc.
2
C hardware