MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2059

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

flexibility for setting up the frame buffers. The LCDIF provides a request signal to the
central DMA if the LCDIF_MASTER bit in HW_LCDIF_CTRL register is 0. The request
signal is asserted any time the LCDIF is enabled and there is at least one data to be read in
its RXFIFO.The DMA request signal is also visible in the LCDIF control and status register.
The DMA reads one word from the HW_LCDIF_DATA register every time it detects a
toggle on the LCDIF request signal.
The CPU can also directly read commands or data by setting up the block in non-bus-master
mode (HW_LCDIF_CTRL_LCDIF_MASTER = 0) and reading directly to the
HW_LCDIF_DATA register without setting up the DMA descriptors. The FIFO status bits
in the HW_LCDIF_STAT register indicate the full and empty states of the RXFIFO. When
the RXFIFO is not empty, the data register can be safely read as required; doing otherwise
will result in an incorrect operation.
33.2.2 Write Datapath
LCDIF expects all frame buffers to be arranged in the raster format since external displays
and digital video encoders require the same. LCDIF directly fetches little-endian data from
memory. This raw input data can be swizzled according to the INPUT_DATA_SWIZZLE
field in the HW_LCDIF_CTRL register before any other operation is performed on the
incoming data. The following four combinations are supported:
The WORD_LENGTH field of HW_LCDIF_CTRL register indicates the input data/pixel
format. HW_LCDIF_TRANSFER_COUNT register denotes how much data is contained
in each frame. The H_COUNT field of this register indicates the number of pixels per line
and V_COUNT indicates the total number of lines per frame. A special bit field in the
HW_LCDIF_CTRL1 register, called the BYTE_PACKING_FORMAT, can be used to
specify which bytes within the 32-bit word are going to be valid. For example, if the entire
32-bit word is valid, BYTE_PACKING_FORMAT should be set to 0xF, if only lower 3
bytes of each word in the frame buffer are valid, then BYTE_PACKING_FORMAT should
be set to 0x7.
The LCD_DATABUS_WIDTH field in HW_LCDIF_CTRL register suggests the width of
the bus going to the external display controller. If the LCD_DATABUS_WIDTH is not the
same as WORD_LENGTH, LCDIF will do minor RGB to RGB color space conversion.
For example, if the input frame has more bits per pixel than the display, for example, 16
bpp input frame going to 24 bpp LCD, LCDIF will pad the MSBs of each color to the LSBs
Freescale Semiconductor, Inc.
00 (0): No swizzle (little-endian)
01 (1): Swap bytes 0 and 3, swap bytes 1 and 2 (big-endian)
10 (2): Swap half-words
11 (3): Swap bytes within each half-word
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 33 LCD Interface (LCDIF)
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