MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2109

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

33.4.25 LCD Interface Data Register (HW_LCDIF_DATA)
The data sent to an external LCD controller is written to this register. Data can be written
to this register (from the processor\'s perspective) as bytes half-words (16 bits) or words
(32 bits) as appropriate.
This register holds the 32-bit word written by either the CPU or the DMA into LCDIF. This
data then gets sent out by the block across the interface. When the block is in bus master
mode, this register gets the value of the lower 32 bits of the 64-bit data bus whenever it is
received.
Address:
Re-
33.4.26 Bus Master Error Status Register
This register reflects the virtual address at which the AXI master received an error response
from the slave.
When the BM_ERROR_IRQ is asserted, the address of the bus error is updated in the
register.
Freescale Semiconductor, Inc.
set
Bit
W
R
DATA_THREE
DATA_ZERO
DATA_TWO
DATA_ONE
31
0
31 24
23 16
Field
15 8
7 0
30
0
DATA_THREE
29
0
HW_LCDIF_DATA
(HW_LCDIF_BM_ERROR_STAT)
28
0
Byte 3 (most significant byte) of data written to LCDIF by the DMA or the CPU.
Byte 2 of data written to LCDIF by the DMA or the CPU.
Byte 1 of data written to LCDIF by the DMA or the CPU.
Byte 0 (least significant byte) of data written to LCDIF by the DMA or the CPU.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
23
0
8003_0000h base + 180h offset = 8003_0180h
HW_LCDIF_DATA field descriptions
22
0
21
0
DATA_TWO
20
0
19
0
18
0
17
0
16
0
15
0
Description
14
0
13
0
DATA_ONE
12
0
11
0
10
0
0
9
Chapter 33 LCD Interface (LCDIF)
0
8
0
7
0
6
DATA_ZERO
0
5
0
4
3
0
0
2
0
1
2109
0
0