MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1553

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

CODE Message Buffer Code
This 4-bit field can be accessed (read or write) by the CPU and by the Flexcan module itself,
as part of the message buffer matching and arbitration process. The encoding is shown in
Table 25-2
Freescale Semiconductor, Inc.
$C
$0
$4
$8
Rx New Frame
Rx Code BE-
31
FORE
0000
0100
0010
0110
PRIO
Data Byte 0
Data Byte 4
and
28
INACTIVE: MB is not active.
EMPTY: MB is active and empty.
FULL: MB is full.
OVERRUN: a frame was overwritten
into a full buffer.
Description
27
Table
CODE
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
ID (Standard/Extended)
Table 25-2. Message Buffer Code for Rx buffers
25-3. See
24
Table 25-1. Message Buffer Structure
SRR
22
Overview
IDE
21
Data Byte 1
Data Byte 5
RTR
20
= Unimplemented or Reserved
19
Rx Code AFTER
Rx New Frame
for additional information.
LENGTH
0010
0010
0110
0010
0110
—
16
15
MB does not participate in the matching process.
MB participates in the matching process. When a
frame is received successfully, the code is auto-
matically updated to FULL.
The act of reading the C/S word followed by unlock-
ing the MB does not make the code return to
EMPTY. It remains FULL. If a new frame is written
to the MB after the C/S word was read and the MB
was unlocked, the code still remains FULL.
If the MB is FULL and a new frame is overwritten
to this MB before the CPU had time to read it, the
code is automatically updated to OVERRUN. Refer
to
havior.
If the code indicates OVERRUN but the CPU reads
the C/S word and then unlocks the MB, when a
new frame is written to the MB the code returns to
FULL.
If the code already indicates OVERRUN, and yet
another new frame must be written, the MB will be
overwritten again, and the code will remain
OVERRUN. Refer to
about overrun behavior.
Chapter 25 Controller Area Network (FlexCAN)
Comment
Matching Process
Data Byte 2
Data Byte 6
ID (Extended)
TIME STAMP
8
Matching Process
for details about overrun be-
7
Data Byte 3
Data Byte 7
for details
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