MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 91
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
- Current page: 91 of 2327
- Download datasheet (17Mb)
Freescale Semiconductor, Inc.
• Six Universal Asynchronous Receiver-Transmitters (UARTs)
• Two I
• Four Synchronous Serial Ports (for SPI, MMC, SDIO, Triflash)
• Four-Channel 32-Bit Timer with Rotary Decoder
• Eight-Channel Pulse Width Modulator (PWM)
• Real-Time Clock
• High-speed memory copy
• Bit Blit
• Five high-speed application UARTs operating up to 3.25 Mb/s with hardware flow
• Debug UART operates at up to 115 Kb/s using programmed I/O
• Up to 400 Kb/s
• DMA control of an entire EEPROM or other device read/write transaction without
• PIO and PIO queue modes controlled by CPU. In PIO queue mode, commands and
• Both 7-bit and 10-bit device address supported in master mode. Programmable
• Up to 52 MHz external SSP clock for SD/MMC mode
• 1-bit, 4-bit and 8-bit MMC/SD/SDIO modes
• Compliant with SDIO Rev. 2.0
• Support eMMC4.3 and eMMC4.4
• SPI with single, dual and quad modes
• Alarm clock can turn the system on
• Uses the existing 24-MHz XTAL for low cost or optional low power crystal (32.768
control, dual DMA and auto baud-rate detection
CPU intervention
data are queued up with FIFOs
7-bit address employed in slave mode
KHz or 32.0 KHz), customer-selectable through OTP
2
C Master/Slave Interfaces
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 1 Product Overview
91
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