MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1539

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

24.3.7 UART Line Control Register, HIGH Byte (HW_UARTDBG_H)
The LCR_H is the Line Control Register.
Address:
Re-
24.3.8 UART Control Register (HW_UARTDBG_CR)
The CR is the Control Register.
Freescale Semiconductor, Inc.
set
Bit
W
R
UNAVAILABLE
Reserved
31
0
31 16
WLEN
STP2
Field
15 8
SPS
FEN
EPS
PEN
BRK
6 5
30
7
4
3
2
1
0
0
29
0
HW_UARTDBG_H
28
0
The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are
always unavailable.
This bitfield is reserved.
Reserved, do not modify, read as zero.
Stick Parity Select. When bits 1, 2, and 7 of the LCR_H register are set, the parity bit is transmitted and
checked as a 0. When bits 1 and 7 are set, and bit 2 is 0, the parity bit is transmitted and checked as a 1.
When this bit is cleared stick parity is disabled.
Word length [1:0]. The select bits indicate the number of data bits transmitted or received in a frame as
follows: 11 = 8 bits, 10 = 7 bits, 01 = 6 bits, 00 = 5 bits.
Enable FIFOs. If this bit is set to 1, transmit and receive FIFO buffers are enabled (FIFO mode). When
cleared to 0, the FIFOs are disabled (character mode); that is, the FIFOs become 1-byte-deep holding
registers.
Two Stop Bits Select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive
logic does not check for two stop bits being received.
Even Parity Select. If this bit is set to 1, even parity generation and checking is performed during transmission
and reception, which checks for an even number of 1s in data and parity bits. When cleared to 0, then odd
parity is performed which checks for an odd number of 1s. This bit has no effect when parity is disabled by
Parity Enable (PEN, bit 1) being cleared to 0.
Parity Enable. If this bit is set to 1, parity checking and generation is enabled, else parity is disabled and no
parity bit added to the data frame.
Send Break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing
transmission of the current character. For the proper execution of the break command, the software must
set this bit for at least two complete frames. For normal use, this bit must be cleared to 0.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
UNAVAILABLE
25
0
24
0
23
0
8007_4000h base + 2Ch offset = 8007_402Ch
HW_UARTDBG_H field descriptions
22
0
21
0
20
0
19
0
18
0
17
0
16
0
15
0
Description
14
0
13
0
RESERVED
12
0
11
0
10
0
0
9
Chapter 24 Debug UART (DUART)
0
8
0
7
0
6
0
5
0
4
3
0
0
2
0
1
1539
0
0