MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1792
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
- Current page: 1792 of 2327
- Download datasheet (17Mb)
Programmable Registers
28.4.8 PWM Channel 3 Active Register (HW_PWM_ACTIVE3)
The PWM Channel 3 Active Register specifies the active time and inactive time for Channel
3.
HW_PWM_ACTIVE3: 0x070
HW_PWM_ACTIVE3_SET: 0x074
HW_PWM_ACTIVE3_CLR: 0x078
HW_PWM_ACTIVE3_TOG: 0x07C
EXAMPLE
HW_PWM_ACTIVEn_WR(3, 0x000000ff);
Address:
Re-
28.4.9 PWM Channel 3 Period Register (HW_PWM_PERIOD3)
The PWM Channel 3 Period Register specifies the multi-chip attachment mode, clock
divider value, active high, low values and period.
HW_PWM_PERIOD3: 0x080
HW_PWM_PERIOD3_SET: 0x084
HW_PWM_PERIOD3_CLR: 0x088
1792
set
Bit
W
R
INACTIVE
31
0
ACTIVE
31 16
Field
15 0
30
0
29
0
HW_PWM_ACTIVE3
28
0
Number of divided clock cycles to count from the beginning of the period before changing the output from
the active state to the inactive state. The internal count of the channel is compared for greater than this
value to change to the inactive state.
Number of divided clock cycles to count from the beginning of the period before changing the output to the
active state. The internal count of the channel is compared for greater than this value to change to the active
state.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
INACTIVE
24
0
23
0
HW_PWM_ACTIVE3 field descriptions
8006_4000h base + 70h offset = 8006_4070h
22
0
21
0
20
0
// Set active and inactive counts
19
0
18
0
17
0
16
0
15
0
Description
14
0
13
0
12
0
11
0
10
0
0
9
ACTIVE
0
8
Freescale Semiconductor, Inc.
0
7
0
6
0
5
0
4
3
0
0
2
0
1
0
0
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