MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1126

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
Address:
Re-
1126
set
Bit
W
AUTO_ENABLE
R
LOWPOWER_
LOWPOWER_
LOWPOWER_
OBSOLETE
REFRESH_
CONTROL
31
0
ENABLE
RSVD3
RSVD2
RSVD1
31 24
23 20
19 16
15 13
Field
12 8
7 5
4 0
30
0
29
0
OBSOLETE
HW_DRAM_CTL22
28
0
Always write zeroes to this field.
Always write zeroes to this field.
Enable refreshes while in low power mode.
Sets whether refreshes will occur while the EMI is in any of the low power modes.
This parameter is active low.
'b0 = Refreshes still occur
'b1 = Refreshes do not occur
Always write zeroes to this field.
Controls entry into the low power modes.
Enables the individual low power modes of the device.
Bit [4] = Controls memory power-down mode (Mode 1).
Bit [3] = Controls memory power-down with memory clock gating mode (Mode 2).
Bit [2] = Controls memory self-refresh mode (Mode 3).
Bit [1] = Controls memory self-refresh with memory clock gating mode (Mode 4).
Bit [0] = Controls memory self-refresh with memory and controller clock gating mode (Mode 5).
For all bits:
'b0 = Disabled.
'b1 = Enabled.
Always write zeroes to this field.
Enables automatic entry into the low power mode on idle.
Enables automatic entry into the low power modes of the EMI.
Bit [4] = Controls memory power-down mode (Mode 1).
Bit [3] = Controls memory power-down with memory clock gating mode (Mode 2).
Bit [2] = Controls memory self-refresh mode (Mode 3).
Bit [1] = Controls memory self-refresh with memory clock gating mode (Mode 4).
Bit [0] = Controls memory self-refresh with memory and controller clock gating mode (Mode 5).
It is not possible to enter Mode 5 manually. Setting bit [0] of lowpower_control with bit [0] of this parameter
cleared will not result in any change.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
23
0
HW_DRAM_CTL22 field descriptions
800E_0000h base + 58h offset = 800E_0058h
RSVD3
22
0
21
0
20
0
19
LOWPOWER_
0
REFRESH_
ENABLE
18
0
17
0
16
0
15
0
Description
RSVD2
14
0
13
0
12
0
LOWPOWER_
CONTROL
11
0
10
0
0
9
0
8
Freescale Semiconductor, Inc.
0
7
RSVD1
0
6
0
5
0
4
AUTO_ENABLE
LOWPOWER_
3
0
0
2
0
1
0
0