MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 350

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Implementation Examples
to the next command to process. NOTE: This is a double indirect case. This method allows
the software to append to a running command list under the protection of the counting
semaphore.
To start processing the first time, software creates the command list to be processed. It
writes the address of the first command into the HW_APBH_CHn_NXTCMDAR register,
and then writes 1 to the counting semaphore in HW_APBH_CHn_SEMA. The DMA channel
loads HW_APBH_CHn_CURCMDAR register and then enters the normal state machine
processing for the next command. When the software writes a value to the counting
semaphore, it is added to the semaphore count by hardware, protecting the case where both
hardware and software are trying to change the semaphore on the same clock edge.
Software can examine the value of HW_APBH_CHn_CURCMDAR at any time to determine
the location of the command structure currently being processed.
6.3 Implementation Examples
6.3.1 NAND Read Status Polling Example
The following figure shows a more complicated scenario. This subset of a NAND device
workload shows that the first two command structures are used during the data-write phase
of an NAND device write operation (CLE and ALE transfers omitted for clarity).
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• After writing the data, one must wait until the NAND device status register indicates
• The NO_DMA_TRANSFER command is shown here performing the read check,
that the write charge has been transferred. This is built into the workload using a check
status command in the NAND in a loop created from the next two DMA command
structures.
followed by a DMA_SENSE command to branch the DMA command structure list,
based on the status of a bit in the external NAND device.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.